org.accellera.ipxact.v1685_2022 package

Subpackages

Submodules

org.accellera.ipxact.v1685_2022.abstraction_def_port_constraints_type module

class org.accellera.ipxact.v1685_2022.abstraction_def_port_constraints_type.AbstractionDefPortConstraintsType(timing_constraint=<factory>, drive_constraint=<factory>, load_constraint=<factory>)

Bases: object

Defines constraints that apply to a wire type port in an abstraction definition.

Parameters:
drive_constraint: Iterable[DriveConstraint]
load_constraint: Iterable[LoadConstraint]
timing_constraint: Iterable[TimingConstraint]

org.accellera.ipxact.v1685_2022.abstraction_definition module

class org.accellera.ipxact.v1685_2022.abstraction_definition.AbstractionDefinition(vendor=None, library=None, name=None, version=None, display_name=None, short_description=None, description=None, bus_type=None, extends=None, ports=None, choices=None, parameters=None, assertions=None, vendor_extensions=None, id=None)

Bases: object

Define the ports and other information of a particular abstraction of the bus.

Variables:

  • vendor – Name of the vendor who supplies this file.

  • library – Name of the logical library this element belongs to.

  • name – The name of the object.

  • version – Indicates the version of the named element.

  • display_name – Name for display purposes. Typically a few words providing a more detailed and/or user-friendly name than the vlnv.

  • short_description

  • description

  • bus_type – Reference to the busDefinition that this abstractionDefinition implements.

  • extends – Optional name of abstraction type that this abstraction definition is compatible with. This abstraction definition may change the definitions of ports in the existing abstraction definition and add new ports, the ports in the original abstraction are not deleted but may be marked illegal to disallow their use. This abstraction definition may only extend another abstraction definition if the bus type of this abstraction definition extends the bus type of the extended abstraction definition

  • ports – This is a list of logical ports defined by the bus.

  • choices

  • parameters

  • assertions

  • vendor_extensions

  • id

Parameters:
class Ports(port: collections.abc.Iterable['AbstractionDefinition.Ports.Port'] = <factory>)

Bases: object

Parameters:

port (Iterable[Port])

class Port(logical_name=None, display_name=None, short_description=None, description=None, match=None, wire=None, transactional=None, packets=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • logical_name – The assigned name of this port in bus specifications.

  • display_name

  • short_description

  • description

  • match – If this element is enabled (true) it is an error if the port is not mapped on both sides of the connection.

  • wire

  • transactional – A port that carries complex information modeled at a high level of abstraction.

  • packets

  • vendor_extensions

  • id

Parameters:
class Transactional(qualifier=None, on_system=<factory>, on_initiator=None, on_target=None)

Bases: object

Variables:

  • qualifier – The type of information this port carries A transactional port can carry both address and data information.

  • on_system – Defines constraints for this port when present in a system bus interface with a matching group name.

  • on_initiator – Defines constraints for this port when present in a initiator bus interface.

  • on_target – Defines constraints for this port when present in a target bus interface.

Parameters:
class OnInitiator(presence=None, initiative=None, kind=None, bus_width=None, protocol=None)

Bases: object

Variables:

  • presence

  • initiative – If this element is present, the type of access is restricted to the specified value.

  • kind

  • bus_width – If this element is present, the width must match

  • protocol – If this element is present, the name must match

Parameters:
bus_width: UnsignedPositiveIntExpression | None
initiative: OnInitiatorInitiative | None
kind: Kind | None
presence: Presence | None
protocol: Protocol | None
class OnSystem(group=None, presence=None, initiative=None, kind=None, bus_width=None, protocol=None, id=None)

Bases: object

Variables:

  • group – Used to group system ports into different groups within a common bus.

  • presence

  • initiative – If this element is present, the type of access is restricted to the specified value.

  • kind

  • bus_width – If this element is present, the width must match

  • protocol – If this element is present, the name must match

  • id

Parameters:
bus_width: UnsignedPositiveIntExpression | None
group: str | None
id: str | None
initiative: OnSystemInitiative | None
kind: Kind | None
presence: Presence | None
protocol: Protocol | None
class OnTarget(presence=None, initiative=None, kind=None, bus_width=None, protocol=None)

Bases: object

Variables:

  • presence

  • initiative – If this element is present, the type of access is restricted to the specified value.

  • kind

  • bus_width – If this element is present, the width must match

  • protocol – If this element is present, the name must match

Parameters:
bus_width: UnsignedPositiveIntExpression | None
initiative: OnTargetInitiative | None
kind: Kind | None
presence: Presence | None
protocol: Protocol | None
on_initiator: OnInitiator | None
on_system: Iterable[OnSystem]
on_target: OnTarget | None
qualifier: QualifierType | None
description: Description | None
display_name: DisplayName | None
id: str | None
logical_name: str | None
match: bool | None
packets: Packets | None
short_description: ShortDescription | None
transactional: Transactional | None
vendor_extensions: VendorExtensions | None
wire: Wire | None
port: Iterable[Port]
assertions: Assertions | None
bus_type: LibraryRefType | None
choices: Choices | None
description: Description | None
display_name: str | None
extends: LibraryRefType | None
id: str | None
library: str | None
name: str | None
parameters: Parameters | None
ports: Ports | None
short_description: ShortDescription | None
vendor: str | None
vendor_extensions: VendorExtensions | None
version: str | None

org.accellera.ipxact.v1685_2022.abstraction_types module

class org.accellera.ipxact.v1685_2022.abstraction_types.AbstractionTypes(abstraction_type=<factory>)

Bases: object

Variables:

abstraction_type – The abstraction type/level of this interface. Refers to abstraction definition using vendor, library, name, version attributes along with any configurable element values needed to configure this abstraction. Bus definition can be found through a reference in this file.

Parameters:

abstraction_type (Iterable[AbstractionType])

class AbstractionType(view_ref=<factory>, abstraction_ref=None, port_maps=None, id=None)

Bases: object

Variables:

  • view_ref – A reference to a view name in the file for which this type applies.

  • abstraction_ref – Provides the VLNV of the abstraction type.

  • port_maps – Listing of maps between component ports and bus ports.

  • id

Parameters:
class PortMaps(port_map=<factory>)

Bases: object

Variables:

port_map – Maps a component’s port to a port in a bus description. This is the logical to physical mapping. The logical pin comes from the bus interface and the physical pin from the component.

Parameters:

port_map (Iterable[PortMap])

class PortMap(logical_port=None, physical_port=None, logical_tie_off=None, is_informative=None, vendor_extensions=None, id=None, invert='false')

Bases: object

Variables:

  • logical_port – Logical port from abstraction definition

  • physical_port – Physical port from this component

  • logical_tie_off – Identifies a value to tie this logical port to.

  • is_informative – When true, indicates that this portMap element is for information purpose only.

  • vendor_extensions

  • id

  • invert – Indicates that the connection between the logical and physical ports should include an inversion.

Parameters:
class LogicalPort(name=None, range=None, id=None)

Bases: object

Variables:

  • name – Bus port name as specified inside the abstraction definition

  • range

  • id

Parameters:

  • name (str | None)

  • range (Range | None)

  • id (str | None)

id: str | None
name: str | None
range: Range | None
class PhysicalPort(name=None, part_select=None, sub_port=<factory>, id=None)

Bases: object

Variables:

  • name – Component port name as specified inside the model port section

  • part_select

  • sub_port

  • id

Parameters:

  • name (str | None)

  • part_select (PartSelect | None)

  • sub_port (Iterable[SubPort])

  • id (str | None)

class SubPort(name=None, part_select=None, id=None)

Bases: object

Variables:

  • name – Component port subPort name as specified inside the model port section

  • part_select

  • id

Parameters:

  • name (str | None)

  • part_select (PartSelect | None)

  • id (str | None)

id: str | None
name: str | None
part_select: PartSelect | None
id: str | None
name: str | None
part_select: PartSelect | None
sub_port: Iterable[SubPort]
id: str | None
invert: object
is_informative: bool | None
logical_port: LogicalPort | None
logical_tie_off: UnsignedBitVectorExpression | None
physical_port: PhysicalPort | None
vendor_extensions: VendorExtensions | None
port_map: Iterable[PortMap]
abstraction_ref: ConfigurableLibraryRefType | None
id: str | None
port_maps: PortMaps | None
view_ref: Iterable[ViewRef]
abstraction_type: Iterable[AbstractionType]

org.accellera.ipxact.v1685_2022.abstractor module

class org.accellera.ipxact.v1685_2022.abstractor.Abstractor(vendor=None, library=None, name=None, version=None, display_name=None, short_description=None, description=None, abstractor_mode=None, bus_type=None, abstractor_interfaces=None, model=None, abstractor_generators=None, choices=None, file_sets=None, parameters=None, assertions=None, vendor_extensions=None, id=None)

Bases: AbstractorType

This is the root element for abstractors.

Parameters:
class AbstractorInterfaces(abstractor_interface=<factory>)

Bases: object

Variables:

abstractor_interface – An abstractor must have exactly 2 Interfaces.

Parameters:

abstractor_interface (Iterable[AbstractorBusInterfaceType])

abstractor_interface: Iterable[AbstractorBusInterfaceType]
class AbstractorMode(value=None, group=None)

Bases: object

Variables:

  • value

  • group – Define the system group if the mode is set to system

Parameters:
group: str | None
value: AbstractorModeType | None
abstractor_generators: AbstractorGenerators | None
abstractor_interfaces: 'AbstractorType.AbstractorInterfaces' | None
abstractor_mode: 'AbstractorType.AbstractorMode' | None
assertions: Assertions | None
bus_type: LibraryRefType | None
choices: Choices | None
description: Description | None
display_name: str | None
file_sets: FileSets | None
id: str | None
library: str | None
model: AbstractorModelType | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
vendor: str | None
vendor_extensions: VendorExtensions | None
version: str | None

org.accellera.ipxact.v1685_2022.abstractor_bus_interface_type module

class org.accellera.ipxact.v1685_2022.abstractor_bus_interface_type.AbstractorBusInterfaceType(name=None, display_name=None, short_description=None, description=None, abstraction_types=None, parameters=None, vendor_extensions=None, id=None, other_attributes=<factory>)

Bases: object

Type definition for a busInterface in a component.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • abstraction_types

  • parameters

  • vendor_extensions

  • id

  • other_attributes

Parameters:
abstraction_types: AbstractionTypes | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
other_attributes: Mapping[str, str]
parameters: Parameters | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.abstractor_generator module

class org.accellera.ipxact.v1685_2022.abstractor_generator.AbstractorGenerator(name=None, display_name=None, short_description=None, description=None, phase=None, parameters=None, api_type=None, api_service=None, transport_methods=None, generator_exe=None, vendor_extensions=None, hidden=False, id=None, group=<factory>, scope=InstanceGeneratorTypeScope.INSTANCE)

Bases: InstanceGeneratorType

Specifies a set of abstractor generators.

The scope attribute applies to abstractor generators and specifies whether the generator should be run for each instance of the entity (or module) or just once for all instances of the entity.

Parameters:
api_service: GeneratorTypeApiService | None
api_type: 'GeneratorType.ApiType' | None
description: Description | None
display_name: DisplayName | None
generator_exe: IpxactUri | None
group: Iterable['InstanceGeneratorType.Group']
hidden: bool
id: str | None
name: str | None
parameters: Parameters | None
phase: Phase | None
scope: InstanceGeneratorTypeScope
short_description: ShortDescription | None
transport_methods: 'GeneratorType.TransportMethods' | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.abstractor_generators module

class org.accellera.ipxact.v1685_2022.abstractor_generators.AbstractorGenerators(abstractor_generator=<factory>)

Bases: object

List of abstractor generators.

Parameters:

abstractor_generator (Iterable[AbstractorGenerator])

abstractor_generator: Iterable[AbstractorGenerator]

org.accellera.ipxact.v1685_2022.abstractor_mode_type module

class org.accellera.ipxact.v1685_2022.abstractor_mode_type.AbstractorModeType(*values)

Bases: Enum

Mode for this abstractor.

DIRECT = 'direct'
INITIATOR = 'initiator'
SYSTEM = 'system'
TARGET = 'target'

org.accellera.ipxact.v1685_2022.abstractor_model_type module

class org.accellera.ipxact.v1685_2022.abstractor_model_type.AbstractorModelType(views=None, instantiations=None, ports=None)

Bases: object

Model information for an abstractor.

Variables:

  • views – Views container

  • instantiations – Instantiations container

  • ports – Port container

Parameters:
class Instantiations(component_instantiation=<factory>)

Bases: object

Variables:

component_instantiation – Component Instantiation

Parameters:

component_instantiation (Iterable[ComponentInstantiationType])

component_instantiation: Iterable[ComponentInstantiationType]
class Ports(port: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.abstractor_port_type.AbstractorPortType] = <factory>)

Bases: object

Parameters:

port (Iterable[AbstractorPortType])

port: Iterable[AbstractorPortType]
class Views(view=<factory>)

Bases: object

Variables:

view – Single view of an abstracto

Parameters:

view (Iterable[View])

class View(name=None, display_name=None, short_description=None, description=None, env_identifier=<factory>, component_instantiation_ref=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • env_identifier – Defines the hardware environment in which this view applies. The format of the string is language:tool:vendor_extension, with each piece being optional. The language must be one of the types from ipxact:fileType. The tool values are defined by the Accellera Systems Initiative, and include generic values “*Simulation” and “*Synthesis” to imply any tool of the indicated type. Having more than one envIdentifier indicates that the view applies to multiple environments.

  • component_instantiation_ref

  • vendor_extensions

  • id

Parameters:
class EnvIdentifier(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
component_instantiation_ref: str | None
description: Description | None
display_name: DisplayName | None
env_identifier: Iterable[EnvIdentifier]
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
view: Iterable[View]
instantiations: Instantiations | None
ports: Ports | None
views: Views | None

org.accellera.ipxact.v1685_2022.abstractor_port_transactional_type module

class org.accellera.ipxact.v1685_2022.abstractor_port_transactional_type.AbstractorPortTransactionalType(initiative=None, kind=None, bus_width=None, qualifier=None, protocol=None, trans_type_defs=None, connection=None, all_logical_initiatives_allowed=False)

Bases: object

Transactional port type.

Variables:

  • initiative – Defines how the port accesses this service.

  • kind – Define the kind of transactional port

  • bus_width – Defines the bus width in bits.This can be the result of an expression.

  • qualifier – The type of information this port carries A transactional port can carry both address and data information.

  • protocol – Defines the protocol type. Defaults to tlm_base_protocol_type for TLM sockets

  • trans_type_defs – Definition of the port type expressed in the default language for this port (i.e. SystemC or SystemV).

  • connection – Bounds number of legal connections.

  • all_logical_initiatives_allowed – True if logical ports with different initiatives from the physical port initiative may be mapped onto this port. Forbidden for phantom ports, which always allow logical ports with all initiatives value to be mapped onto the physical port. Also ignored for “both” ports, since any logical port may be mapped to a physical “both” port.

Parameters:
class Connection(max_connections=None, min_connections=None)

Bases: object

Variables:

  • max_connections – Indicates the maximum number of connections this port supports. If this element is not present or set to 0 it implies an unbounded number of allowed connections.

  • min_connections – Indicates the minimum number of connections this port supports. If this element is not present, the minimum number of allowed connections is 1.

Parameters:
max_connections: UnsignedIntExpression | None
min_connections: UnsignedIntExpression | None
all_logical_initiatives_allowed: bool
bus_width: BusWidth | None
connection: Connection | None
initiative: Initiative | None
kind: Kind | None
protocol: Protocol | None
qualifier: QualifierType | None
trans_type_defs: TransTypeDefs | None

org.accellera.ipxact.v1685_2022.abstractor_port_type module

class org.accellera.ipxact.v1685_2022.abstractor_port_type.AbstractorPortType(name=None, display_name=None, short_description=None, description=None, wire=None, transactional=None, structured=None, arrays=None, access=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

A port description, giving a name and an access type for high level ports.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • wire – Defines a port whose type resolves to simple bits.

  • transactional – Defines a port that implements or uses a service that can be implemented with functions or methods.

  • structured – Represents a port that has subport structure.

  • arrays

  • access – Port access characteristics.

  • parameters

  • vendor_extensions

  • id

Parameters:
access: PortAccessType1 | None
arrays: Arrays | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
structured: AbstractorPortStructuredType | None
transactional: AbstractorPortTransactionalType | None
vendor_extensions: VendorExtensions | None
wire: AbstractorPortWireType | None

org.accellera.ipxact.v1685_2022.abstractor_port_wire_type module

class org.accellera.ipxact.v1685_2022.abstractor_port_wire_type.AbstractorPortWireType(direction=None, qualifier=None, vectors=None, wire_type_defs=None, domain_type_defs=None, signal_type_defs=None, drivers=None, all_logical_directions_allowed=False)

Bases: PortWireType

Wire port type for an abstractor.

Variables:

  • constraint_sets

  • power_constraints – Wire port power constraints.

Parameters:
class PowerConstraints(power_constraint=<factory>)

Bases: object

Variables:

power_constraint – Single wire port set of power constraints.

Parameters:

power_constraint (Iterable[WirePowerConstraintType])

power_constraint: Iterable[WirePowerConstraintType]
all_logical_directions_allowed: bool
constraint_sets: Any
direction: ComponentPortDirectionType | None
domain_type_defs: DomainTypeDefs | None
drivers: Drivers | None
power_constraints: Any
qualifier: QualifierType | None
signal_type_defs: SignalTypeDefs | None
vectors: ExtendedVectorsType | None
wire_type_defs: WireTypeDefs | None

org.accellera.ipxact.v1685_2022.abstractor_sub_port_type module

class org.accellera.ipxact.v1685_2022.abstractor_sub_port_type.AbstractorPortStructuredType(struct=None, union=None, interface=None, vectors=None, sub_ports=None, struct_port_type_defs=None, packed=True)

Bases: object

Variables:

  • struct

  • union

  • interface

  • vectors – Vectored information.

  • sub_ports

  • struct_port_type_defs

  • packed – When not present or set to ‘true’ indicates that this structured port is ‘packed’. If present and set to ‘false’, indicates that this structured port is ‘unpacked’.

Parameters:
class Interface(phantom: bool | None = None)

Bases: object

Parameters:

phantom (bool | None)

phantom: bool | None
class Struct(direction=None)

Bases: object

Variables:

direction – The direction of a wire style port. The basic directions for a port are ‘in’ for input ports, ‘out’ for output port and ‘inout’ for bidirectional and tristate ports. A value of ‘phantom’ is also allowed and define a port that exist on the IP-XACT component but not on the HDL model.

Parameters:

direction (ComponentPortDirectionType | None)

direction: ComponentPortDirectionType | None
class SubPorts(sub_port: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.abstractor_sub_port_type.AbstractorSubPortType] = <factory>)

Bases: object

Parameters:

sub_port (Iterable[AbstractorSubPortType])

sub_port: Iterable[AbstractorSubPortType]
class UnionType(direction=None)

Bases: object

Variables:

direction – The direction of a wire style port. The basic directions for a port are ‘in’ for input ports, ‘out’ for output port and ‘inout’ for bidirectional and tristate ports. A value of ‘phantom’ is also allowed and define a port that exist on the IP-XACT component but not on the HDL model.

Parameters:

direction (ComponentPortDirectionType | None)

direction: ComponentPortDirectionType | None
interface: Interface | None
packed: bool
struct: Struct | None
struct_port_type_defs: StructPortTypeDefs | None
sub_ports: SubPorts | None
union: UnionType | None
vectors: ExtendedVectorsType | None
class org.accellera.ipxact.v1685_2022.abstractor_sub_port_type.AbstractorSubPortType(name=None, display_name=None, short_description=None, description=None, wire=None, structured=None, arrays=None, access=None, vendor_extensions=None, id=None, is_io=None)

Bases: object

A port description, giving a name and an access type for high level ports.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • wire – Defines a port whose type resolves to simple bits.

  • structured

  • arrays

  • access – Port access characteristics.

  • vendor_extensions

  • id

  • is_io – When present and set to ‘true’ identifies this port as being an I/O to the containing structure port type. Only valid for subPorts contained in a structured port with structType=’interface’.

Parameters:
access: PortAccessType1 | None
arrays: Arrays | None
description: Description | None
display_name: DisplayName | None
id: str | None
is_io: bool | None
name: str | None
short_description: ShortDescription | None
structured: AbstractorPortStructuredType | None
vendor_extensions: VendorExtensions | None
wire: AbstractorPortWireType | None

org.accellera.ipxact.v1685_2022.abstractor_type module

class org.accellera.ipxact.v1685_2022.abstractor_type.AbstractorType(vendor=None, library=None, name=None, version=None, display_name=None, short_description=None, description=None, abstractor_mode=None, bus_type=None, abstractor_interfaces=None, model=None, abstractor_generators=None, choices=None, file_sets=None, parameters=None, assertions=None, vendor_extensions=None, id=None)

Bases: object

Abstractor-specific extension to abstractorType.

Variables:

  • vendor – Name of the vendor who supplies this file.

  • library – Name of the logical library this element belongs to.

  • name – The name of the object.

  • version – Indicates the version of the named element.

  • display_name – Name for display purposes. Typically a few words providing a more detailed and/or user-friendly name than the vlnv.

  • short_description

  • description

  • abstractor_mode – Define the mode for the interfaces on this abstractor. For initiator the first interface connects to the initiator, the second connects to the mirroredInitiator For target the first interface connects to the mirroredTarget the second connects to the target For direct the first interface connects to the initiator, the second connects to the target For system the first interface connects to the system, the second connects to the mirroredSystem. For system the group attribute is required

  • bus_type – The bus type of both interfaces. Refers to bus definition using vendor, library, name, version attributes.

  • abstractor_interfaces – The interfaces supported by this abstractor

  • model – Model information.

  • abstractor_generators – Generator list is tools-specific.

  • choices

  • file_sets

  • parameters

  • assertions

  • vendor_extensions

  • id

Parameters:
class AbstractorInterfaces(abstractor_interface=<factory>)

Bases: object

Variables:

abstractor_interface – An abstractor must have exactly 2 Interfaces.

Parameters:

abstractor_interface (Iterable[AbstractorBusInterfaceType])

abstractor_interface: Iterable[AbstractorBusInterfaceType]
class AbstractorMode(value=None, group=None)

Bases: object

Variables:

  • value

  • group – Define the system group if the mode is set to system

Parameters:
group: str | None
value: AbstractorModeType | None
abstractor_generators: AbstractorGenerators | None
abstractor_interfaces: AbstractorInterfaces | None
abstractor_mode: AbstractorMode | None
assertions: Assertions | None
bus_type: LibraryRefType | None
choices: Choices | None
description: Description | None
display_name: str | None
file_sets: FileSets | None
id: str | None
library: str | None
model: AbstractorModelType | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
vendor: str | None
vendor_extensions: VendorExtensions | None
version: str | None

org.accellera.ipxact.v1685_2022.access module

class org.accellera.ipxact.v1685_2022.access.Access(value: org.accellera.ipxact.v1685_2022.access_type.AccessType | None = None)

Bases: object

Parameters:

value (AccessType | None)

value: AccessType | None

org.accellera.ipxact.v1685_2022.access_policies module

class org.accellera.ipxact.v1685_2022.access_policies.AccessPolicies(access_policy: collections.abc.Iterable['AccessPolicies.AccessPolicy'] = <factory>)

Bases: object

Parameters:

access_policy (Iterable[AccessPolicy])

class AccessPolicy(mode_ref: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.mode_ref.ModeRef] = <factory>, access: Optional[org.accellera.ipxact.v1685_2022.access_type.AccessType] = None, vendor_extensions: Optional[org.accellera.ipxact.v1685_2022.vendor_extensions.VendorExtensions] = None, id: Optional[str] = None)

Bases: object

Parameters:

  • mode_ref (Iterable[ModeRef])

  • access (AccessType | None)

  • vendor_extensions (VendorExtensions | None)

  • id (str | None)

access: AccessType | None
id: str | None
mode_ref: Iterable[ModeRef]
vendor_extensions: VendorExtensions | None
access_policy: Iterable[AccessPolicy]

org.accellera.ipxact.v1685_2022.access_properties_type module

class org.accellera.ipxact.v1685_2022.access_properties_type.AccessPropertiesType(access_entry_type_ref=None, id=None)

Bases: object

Variables:

  • access_entry_type_ref – Reference to a user defined accessEntryType. Assumed to be DEFAULT if not present.

  • id

Parameters:

  • access_entry_type_ref (str | None)

  • id (str | None)

access_entry_type_ref: str | None
id: str | None

org.accellera.ipxact.v1685_2022.access_restriction_type module

class org.accellera.ipxact.v1685_2022.access_restriction_type.AccessRestrictionType(mode_ref=<factory>, read_access_mask=None, write_access_mask=None, id=None)

Bases: object

Variables:

  • mode_ref

  • read_access_mask – Mask to be anded with the readable bits in this field to determine the readabe bits in this access mode. If not present, the value defaults to “all ones” meaning that read access is not blocked.

  • write_access_mask – Mask to be anded with the writable bits in this field to determine the writeable bits in this access mode. If not present, the value defaults to “all ones” meaning that write access is not blocked.

  • id

Parameters:
id: str | None
mode_ref: Iterable[ModeRef]
read_access_mask: UnsignedBitVectorExpression | None
write_access_mask: UnsignedBitVectorExpression | None

org.accellera.ipxact.v1685_2022.access_restrictions module

class org.accellera.ipxact.v1685_2022.access_restrictions.AccessRestrictions(access_restriction=<factory>)

Bases: AccessRestrictionsType

Access modes.

Parameters:

access_restriction (Iterable[AccessRestrictionType])

access_restriction: Iterable[AccessRestrictionType]

org.accellera.ipxact.v1685_2022.access_restrictions_type module

class org.accellera.ipxact.v1685_2022.access_restrictions_type.AccessRestrictionsType(access_restriction=<factory>)

Bases: object

Variables:

access_restriction – Access mode.

Parameters:

access_restriction (Iterable[AccessRestrictionType])

access_restriction: Iterable[AccessRestrictionType]

org.accellera.ipxact.v1685_2022.access_type module

org.accellera.ipxact.v1685_2022.active_interface module

class org.accellera.ipxact.v1685_2022.active_interface.ActiveInterface(component_instance_ref=None, bus_ref=None, id=None, description=None, exclude_ports=None, vendor_extensions=None)

Bases: InterfaceType

Variables:

  • description

  • exclude_ports – The list of physical ports to be excluded from an interface based connection. Analogous to the removing the port map element for the named ports.

  • vendor_extensions

Parameters:
class ExcludePorts(exclude_port=<factory>)

Bases: object

Variables:

exclude_port – The name of a physical port to be excluded from the interface based connection.

Parameters:

exclude_port (Iterable[ExcludePort])

class ExcludePort(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
exclude_port: Iterable[ExcludePort]
bus_ref: str | None
component_instance_ref: str | None
description: Description | None
exclude_ports: ExcludePorts | None
id: str | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.ad_hoc_connection module

class org.accellera.ipxact.v1685_2022.ad_hoc_connection.AdHocConnection(name=None, display_name=None, short_description=None, description=None, tied_value=None, port_references=None, vendor_extensions=None, id=None)

Bases: object

Represents an ad-hoc connection between component ports.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • tied_value – The logic value of this connection. The value can be an unsigned bit vector expression or the string values ‘open’ or ‘default’. Only valid for ports of style wire.

  • port_references – Liist of internal and external port references involved in the adhocConnection

  • vendor_extensions

  • id

Parameters:
class PortReferences(internal_port_reference=<factory>, external_port_reference=<factory>)

Bases: object

Variables:

  • internal_port_reference – Defines a reference to a port on a component contained within the design.

  • external_port_reference

Parameters:
class InternalPortReference(sub_port_reference=<factory>, part_select=None, vendor_extensions=None, port_ref=None, component_instance_ref=None, id=None)

Bases: object

Variables:

  • sub_port_reference

  • part_select

  • vendor_extensions

  • port_ref – A port on the on the referenced component from componentInterfaceRef.

  • component_instance_ref – A reference to the instanceName element of a component in this design.

  • id

Parameters:
component_instance_ref: str | None
id: str | None
part_select: PartSelect | None
port_ref: str | None
sub_port_reference: Iterable[SubPortReference]
vendor_extensions: VendorExtensions | None
external_port_reference: Iterable[ExternalPortReference]
internal_port_reference: Iterable[InternalPortReference]
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
port_references: PortReferences | None
short_description: ShortDescription | None
tied_value: ComplexTiedValueExpression | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.ad_hoc_connections module

class org.accellera.ipxact.v1685_2022.ad_hoc_connections.AdHocConnections(ad_hoc_connection=<factory>)

Bases: object

Defines the set of ad-hoc connections in a design.

An ad-hoc connection represents a connection between two component pins which were not connected as a result of interface connections (i.e.the pin to pin connection was made explicitly and is represented explicitly).

Parameters:

ad_hoc_connection (Iterable[AdHocConnection])

ad_hoc_connection: Iterable[AdHocConnection]

org.accellera.ipxact.v1685_2022.addr_space_ref_type module

class org.accellera.ipxact.v1685_2022.addr_space_ref_type.AddrSpaceRefType(vendor_extensions=None, address_space_ref=None, id=None)

Bases: object

Base type for an element which references an address space.

Reference is kept in an attribute rather than the text value, so that the type may be extended with child elements if necessary.

Variables:

  • vendor_extensions

  • address_space_ref – A reference to a unique address space.

  • id

Parameters:

  • vendor_extensions (VendorExtensions | None)

  • address_space_ref (str | None)

  • id (str | None)

address_space_ref: str | None
id: str | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.address_bank_definition_type module

class org.accellera.ipxact.v1685_2022.address_bank_definition_type.AddressBankDefinitionType(name=None, display_name=None, short_description=None, description=None, access_handles=None, base_address=None, bank_definition_ref=None, address_block=<factory>, bank=<factory>, usage=None, volatile=None, access_policies=None, parameters=None, vendor_extensions=None, bank_alignment=None, id=None)

Bases: object

Top level bank the specify an address.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • base_address

  • bank_definition_ref

  • address_block – An address block within the bank. No address information is supplied.

  • bank – A nested bank of blocks within a bank. No address information is supplied.

  • usage – Indicates the usage of this block. Possible values are ‘memory’, ‘register’ and ‘reserved’.

  • volatile

  • access_policies

  • parameters – Any additional parameters needed to describe this address block to the generators.

  • vendor_extensions

  • bank_alignment – Describes whether this bank’s blocks are aligned in ‘parallel’ or ‘serial’.

  • id

Parameters:
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_block: Iterable[BankedBlockType]
bank: Iterable[Bank]
bank_alignment: BankAlignmentType | None
bank_definition_ref: BankDefinitionRef | None
base_address: BaseAddress | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
usage: UsageType | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None

org.accellera.ipxact.v1685_2022.address_bank_type module

class org.accellera.ipxact.v1685_2022.address_bank_type.AddressBankType(name=None, display_name=None, short_description=None, description=None, access_handles=None, base_address=None, bank_definition_ref=None, address_block=<factory>, bank=<factory>, subspace_map=<factory>, usage=None, volatile=None, access_policies=None, parameters=None, vendor_extensions=None, bank_alignment=None, id=None)

Bases: object

Top level bank the specify an address.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • base_address

  • bank_definition_ref

  • address_block – An address block within the bank. No address information is supplied.

  • bank – A nested bank of blocks within a bank. No address information is supplied.

  • subspace_map – A subspace map within the bank. No address information is supplied.

  • usage – Indicates the usage of this block. Possible values are ‘memory’, ‘register’ and ‘reserved’.

  • volatile

  • access_policies

  • parameters – Any additional parameters needed to describe this address block to the generators.

  • vendor_extensions

  • bank_alignment – Describes whether this bank’s blocks are aligned in ‘parallel’ or ‘serial’.

  • id

Parameters:
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_block: Iterable[BankedBlockType]
bank: Iterable[Bank]
bank_alignment: BankAlignmentType | None
bank_definition_ref: BankDefinitionRef | None
base_address: BaseAddress | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
subspace_map: Iterable[BankedSubspaceType]
usage: UsageType | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None

org.accellera.ipxact.v1685_2022.address_block module

class org.accellera.ipxact.v1685_2022.address_block.AddressBlock(name=None, display_name=None, short_description=None, description=None, access_handles=None, array=None, base_address=None, address_block_definition_ref=None, type_identifier=None, range=None, width=None, usage=None, volatile=None, access_policies=None, parameters=None, register=<factory>, register_file=<factory>, vendor_extensions=None, id=None, misalignment_allowed=True)

Bases: AddressBlockType

This is a single contiguous block of memory inside a memory map.

Parameters:
class AddressBlockDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
class Register(name=None, display_name=None, short_description=None, description=None, access_handles=None, array=None, address_offset=None, register_definition_ref=None, type_identifier=None, size=None, volatile=None, access_policies=None, field_value=<factory>, alternate_registers=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • array

  • address_offset – Offset from the address block’s baseAddress or the containing register file’s addressOffset, expressed as the number of addressUnitBits from the containing memoryMap or localMemoryMap.

  • register_definition_ref

  • type_identifier – Identifier name used to indicate that multiple register elements contain the exact same information for the elements in the registerDefinitionGroup.

  • size – Width of the register in bits.

  • volatile

  • access_policies

  • field_value – Describes individual bit fields within the register.

  • alternate_registers

  • parameters

  • vendor_extensions

  • id

Parameters:
class RegisterDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_offset: UnsignedLongintExpression | None
alternate_registers: AlternateRegisters | None
array: Array | None
description: Description | None
display_name: DisplayName | None
field_value: Iterable[FieldType]
id: str | None
name: str | None
parameters: Parameters | None
register_definition_ref: RegisterDefinitionRef | None
short_description: ShortDescription | None
size: UnsignedPositiveIntExpression | None
type_identifier: str | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
access_handles: 'AddressBlockType.AccessHandles' | None
access_policies: AccessPolicies | None
address_block_definition_ref: 'AddressBlockType.AddressBlockDefinitionRef' | None
array: Array | None
base_address: BaseAddress | None
description: Description | None
display_name: DisplayName | None
id: str | None
misalignment_allowed: bool
name: str | None
parameters: Parameters | None
range: UnsignedPositiveLongintExpression | None
register: Iterable['AddressBlockType.Register']
register_file: Iterable[RegisterFile]
short_description: ShortDescription | None
type_identifier: str | None
usage: UsageType | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
width: UnsignedPositiveIntExpression | None

org.accellera.ipxact.v1685_2022.address_block_definitions module

class org.accellera.ipxact.v1685_2022.address_block_definitions.AddressBlockDefinitions(address_block_definition: collections.abc.Iterable['AddressBlockDefinitions.AddressBlockDefinition'] = <factory>)

Bases: object

Parameters:

address_block_definition (Iterable[AddressBlockDefinition])

class AddressBlockDefinition(name=None, display_name=None, short_description=None, description=None, type_identifier=None, range=None, width=None, usage=None, volatile=None, access_policies=None, parameters=None, register=<factory>, register_file=<factory>, address_unit_bits=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • type_identifier – Identifier name used to indicate that multiple addressBlock elements contain the exact same information except for the elements in the addressBlockInstanceGroup.

  • range – The address range of an address block. Expressed as the number of addressable units accessible to the block. The range and the width are related by the following formulas: number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range number_of_rows_in_block = number_of_bits_in_block / ipxact:width

  • width – The bit width of a row in the address block. The range and the width are related by the following formulas: number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range number_of_rows_in_block = number_of_bits_in_block / ipxact:width

  • usage – Indicates the usage of this block. Possible values are ‘memory’, ‘register’ and ‘reserved’.

  • volatile

  • access_policies

  • parameters – Any additional parameters needed to describe this address block to the generators.

  • register – A single register

  • register_file – A structure of registers and register files

  • address_unit_bits

  • vendor_extensions

  • id

Parameters:
class Register(name=None, display_name=None, short_description=None, description=None, access_handles=None, array=None, address_offset=None, register_definition_ref=None, type_identifier=None, size=None, volatile=None, access_policies=None, field_value=<factory>, alternate_registers=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • array

  • address_offset – Offset from the address block’s baseAddress or the containing register file’s addressOffset, expressed as the number of addressUnitBits from the containing memoryMap or localMemoryMap.

  • register_definition_ref

  • type_identifier – Identifier name used to indicate that multiple register elements contain the exact same information for the elements in the registerDefinitionGroup.

  • size – Width of the register in bits.

  • volatile

  • access_policies

  • field_value – Describes individual bit fields within the register.

  • alternate_registers

  • parameters

  • vendor_extensions

  • id

Parameters:
class RegisterDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_offset: UnsignedLongintExpression | None
alternate_registers: AlternateRegisters | None
array: Array | None
description: Description | None
display_name: DisplayName | None
field_value: Iterable[FieldType]
id: str | None
name: str | None
parameters: Parameters | None
register_definition_ref: RegisterDefinitionRef | None
short_description: ShortDescription | None
size: UnsignedPositiveIntExpression | None
type_identifier: str | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
access_policies: AccessPolicies | None
address_unit_bits: AddressUnitBits | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
range: UnsignedPositiveLongintExpression | None
register: Iterable[Register]
register_file: Iterable[RegisterFile]
short_description: ShortDescription | None
type_identifier: str | None
usage: UsageType | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
width: UnsignedPositiveIntExpression | None
address_block_definition: Iterable[AddressBlockDefinition]

org.accellera.ipxact.v1685_2022.address_block_ref module

class org.accellera.ipxact.v1685_2022.address_block_ref.AddressBlockRef(indices: org.accellera.ipxact.v1685_2022.indices.Indices | None = None, address_block_ref: str | None = None)

Bases: object

Parameters:

  • indices (Indices | None)

  • address_block_ref (str | None)

address_block_ref: str | None
indices: Indices | None

org.accellera.ipxact.v1685_2022.address_block_type module

class org.accellera.ipxact.v1685_2022.address_block_type.AddressBlockType(name=None, display_name=None, short_description=None, description=None, access_handles=None, array=None, base_address=None, address_block_definition_ref=None, type_identifier=None, range=None, width=None, usage=None, volatile=None, access_policies=None, parameters=None, register=<factory>, register_file=<factory>, vendor_extensions=None, id=None, misalignment_allowed=True)

Bases: object

Top level address block that specify an address.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • array

  • base_address

  • address_block_definition_ref

  • type_identifier – Identifier name used to indicate that multiple addressBlock elements contain the exact same information except for the elements in the addressBlockInstanceGroup.

  • range – The address range of an address block. Expressed as the number of addressable units accessible to the block. The range and the width are related by the following formulas: number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range number_of_rows_in_block = number_of_bits_in_block / ipxact:width

  • width – The bit width of a row in the address block. The range and the width are related by the following formulas: number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range number_of_rows_in_block = number_of_bits_in_block / ipxact:width

  • usage – Indicates the usage of this block. Possible values are ‘memory’, ‘register’ and ‘reserved’.

  • volatile

  • access_policies

  • parameters – Any additional parameters needed to describe this address block to the generators.

  • register – A single register

  • register_file – A structure of registers and register files

  • vendor_extensions

  • id

  • misalignment_allowed – If true, register alignment is not restricted to register size. Defaults to false.

Parameters:
class AddressBlockDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
class Register(name=None, display_name=None, short_description=None, description=None, access_handles=None, array=None, address_offset=None, register_definition_ref=None, type_identifier=None, size=None, volatile=None, access_policies=None, field_value=<factory>, alternate_registers=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • array

  • address_offset – Offset from the address block’s baseAddress or the containing register file’s addressOffset, expressed as the number of addressUnitBits from the containing memoryMap or localMemoryMap.

  • register_definition_ref

  • type_identifier – Identifier name used to indicate that multiple register elements contain the exact same information for the elements in the registerDefinitionGroup.

  • size – Width of the register in bits.

  • volatile

  • access_policies

  • field_value – Describes individual bit fields within the register.

  • alternate_registers

  • parameters

  • vendor_extensions

  • id

Parameters:
class RegisterDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_offset: UnsignedLongintExpression | None
alternate_registers: AlternateRegisters | None
array: Array | None
description: Description | None
display_name: DisplayName | None
field_value: Iterable[FieldType]
id: str | None
name: str | None
parameters: Parameters | None
register_definition_ref: RegisterDefinitionRef | None
short_description: ShortDescription | None
size: UnsignedPositiveIntExpression | None
type_identifier: str | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_block_definition_ref: AddressBlockDefinitionRef | None
array: Array | None
base_address: BaseAddress | None
description: Description | None
display_name: DisplayName | None
id: str | None
misalignment_allowed: bool
name: str | None
parameters: Parameters | None
range: UnsignedPositiveLongintExpression | None
register: Iterable[Register]
register_file: Iterable[RegisterFile]
short_description: ShortDescription | None
type_identifier: str | None
usage: UsageType | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
width: UnsignedPositiveIntExpression | None

org.accellera.ipxact.v1685_2022.address_spaces module

class org.accellera.ipxact.v1685_2022.address_spaces.AddressSpaces(address_space=<factory>)

Bases: object

If this component is a bus initiator, this lists all the address spaces defined by the component.

Variables:

address_space – This defines a logical space, referenced by a bus initiator.

Parameters:

address_space (Iterable[AddressSpace])

class AddressSpace(name=None, display_name=None, short_description=None, description=None, range=None, width=None, segments=None, address_unit_bits=None, local_memory_map=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • range – The address range of an address block. Expressed as the number of addressable units accessible to the block. The range and the width are related by the following formulas: number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range number_of_rows_in_block = number_of_bits_in_block / ipxact:width

  • width – The bit width of a row in the address block. The range and the width are related by the following formulas: number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range number_of_rows_in_block = number_of_bits_in_block / ipxact:width

  • segments – Address segments withing an addressSpace

  • address_unit_bits

  • local_memory_map – Provides the local memory map of an address space. Blocks in this memory map are accessable to initiator interfaces on this component that reference this address space. They are not accessable to any external initiator interface.

  • parameters – Data specific to this address space.

  • vendor_extensions

  • id

Parameters:
class Segments(segment=<factory>)

Bases: object

Variables:

segment – Address segment withing an addressSpace

Parameters:

segment (Iterable[Segment])

class Segment(name=None, display_name=None, short_description=None, description=None, address_offset=None, range=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • address_offset – Address offset of the segment within the containing address space.

  • range – The address range of asegment. Expressed as the number of addressable units accessible to the segment.

  • vendor_extensions

  • id

Parameters:
address_offset: UnsignedLongintExpression | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
range: UnsignedPositiveLongintExpression | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
segment: Iterable[Segment]
address_unit_bits: AddressUnitBits | None
description: Description | None
display_name: DisplayName | None
id: str | None
local_memory_map: LocalMemoryMapType | None
name: str | None
parameters: Parameters | None
range: UnsignedPositiveLongintExpression | None
segments: Segments | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
width: UnsignedPositiveIntExpression | None
address_space: Iterable[AddressSpace]

org.accellera.ipxact.v1685_2022.address_unit_bits module

class org.accellera.ipxact.v1685_2022.address_unit_bits.AddressUnitBits(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: UnsignedPositiveLongintExpression

The number of data bits in an addressable unit.

The default is byte addressable (8 bits).

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.alternate_register_ref module

class org.accellera.ipxact.v1685_2022.alternate_register_ref.AlternateRegisterRef(alternate_register_ref: str | None = None)

Bases: object

Parameters:

alternate_register_ref (str | None)

alternate_register_ref: str | None

org.accellera.ipxact.v1685_2022.alternate_registers module

class org.accellera.ipxact.v1685_2022.alternate_registers.AlternateRegisters(alternate_register=<factory>)

Bases: object

Alternate definitions for the current register.

Variables:

alternate_register – Alternate definition for the current register

Parameters:

alternate_register (Iterable[AlternateRegister])

class AlternateRegister(name=None, display_name=None, short_description=None, description=None, access_handles=None, mode_ref=<factory>, type_identifier=None, volatile=None, access_policies=None, field_value=<factory>, parameters=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • mode_ref

  • type_identifier – Identifier name used to indicate that multiple register elements contain the exact same information for the elements in the alternateRegisterDefinitionGroup.

  • volatile

  • access_policies

  • field_value – Describes individual bit fields within the register.

  • parameters

  • vendor_extensions

  • id

Parameters:
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
description: Description | None
display_name: DisplayName | None
field_value: Iterable[FieldType]
id: str | None
mode_ref: Iterable[ModeRef]
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
type_identifier: str | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
alternate_register: Iterable[AlternateRegister]

org.accellera.ipxact.v1685_2022.always_on module

class org.accellera.ipxact.v1685_2022.always_on.AlwaysOn(value='', other_attributes=<factory>)

Bases: UnsignedBitExpression

Boolean value.

If set to true, then the domain/port is always powered, whatever its power domain. Only applies for output ports.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.api_type module

org.accellera.ipxact.v1685_2022.array module

class org.accellera.ipxact.v1685_2022.array.Array(dim=<factory>, stride=None)

Bases: object

Variables:

  • dim – Dimensions a memory-map element array, the semantics for dim elements are the same as the C language standard for the layout of memory in multidimensional arrays.

  • stride

Parameters:
dim: Iterable[Dim]
stride: Stride | None

org.accellera.ipxact.v1685_2022.arrays module

class org.accellera.ipxact.v1685_2022.arrays.Arrays(array=<factory>)

Bases: object

Variables:

array – Specific left and right array bounds.

Parameters:

array (Iterable[Array])

class Array(left: org.accellera.ipxact.v1685_2022.left.Left | None = None, right: org.accellera.ipxact.v1685_2022.right.Right | None = None, array_id: str | None = None, id: str | None = None)

Bases: object

Parameters:

  • left (Left | None)

  • right (Right | None)

  • array_id (str | None)

  • id (str | None)

array_id: str | None
id: str | None
left: Left | None
right: Right | None
array: Iterable[Array]

org.accellera.ipxact.v1685_2022.assertion module

class org.accellera.ipxact.v1685_2022.assertion.Assertion(name=None, display_name=None, short_description=None, description=None, assert_value=None, id=None)

Bases: object

Provides an expression for describing valid parameter value settings.

If a assertion assert expression evaluates false, the name, displayName and/or description can be used to communicate the assertion failure.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • assert_value

  • id

Parameters:
assert_value: UnsignedBitExpression | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None

org.accellera.ipxact.v1685_2022.assertions module

class org.accellera.ipxact.v1685_2022.assertions.Assertions(assertion=<factory>)

Bases: object

List of assertions about allowed parameter values.

Parameters:

assertion (Iterable[Assertion])

assertion: Iterable[Assertion]

org.accellera.ipxact.v1685_2022.bank module

org.accellera.ipxact.v1685_2022.bank_alignment_type module

class org.accellera.ipxact.v1685_2022.bank_alignment_type.BankAlignmentType(*values)

Bases: Enum

‘serial’ or ‘parallel’ bank alignment.

PARALLEL = 'parallel'
SERIAL = 'serial'

org.accellera.ipxact.v1685_2022.bank_definitions module

class org.accellera.ipxact.v1685_2022.bank_definitions.BankDefinitions(bank_definition: collections.abc.Iterable['BankDefinitions.BankDefinition'] = <factory>)

Bases: object

Parameters:

bank_definition (Iterable[BankDefinition])

class BankDefinition(name=None, display_name=None, short_description=None, description=None, address_block=<factory>, bank=<factory>, usage=None, volatile=None, access_policies=None, parameters=None, address_unit_bits=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • address_block – An address block within the bank. No address information is supplied.

  • bank – A nested bank of blocks within a bank. No address information is supplied.

  • usage – Indicates the usage of this block. Possible values are ‘memory’, ‘register’ and ‘reserved’.

  • volatile

  • access_policies

  • parameters – Any additional parameters needed to describe this address block to the generators.

  • address_unit_bits

  • vendor_extensions

  • id

Parameters:
access_policies: AccessPolicies | None
address_block: Iterable[BankedBlockType]
address_unit_bits: AddressUnitBits | None
bank: Iterable[Bank]
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
usage: UsageType | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
bank_definition: Iterable[BankDefinition]

org.accellera.ipxact.v1685_2022.bank_ref module

class org.accellera.ipxact.v1685_2022.bank_ref.BankRef(bank_ref: str | None = None, id: str | None = None)

Bases: object

Parameters:

  • bank_ref (str | None)

  • id (str | None)

bank_ref: str | None
id: str | None

org.accellera.ipxact.v1685_2022.banked_bank_type module

class org.accellera.ipxact.v1685_2022.banked_bank_type.BankedBankType(name=None, display_name=None, short_description=None, description=None, access_handles=None, bank_definition_ref=None, address_block=<factory>, bank=<factory>, subspace_map=<factory>, usage=None, volatile=None, access_policies=None, parameters=None, bank_alignment=None, id=None)

Bases: object

Banks nested inside a bank do not specify address.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • bank_definition_ref

  • address_block – An address block within the bank. No address information is supplied.

  • bank – A nested bank of blocks within a bank. No address information is supplied.

  • subspace_map – A subspace map within the bank. No address information is supplied.

  • usage – Indicates the usage of this block. Possible values are ‘memory’, ‘register’ and ‘reserved’.

  • volatile

  • access_policies

  • parameters – Any additional parameters needed to describe this address block to the generators.

  • bank_alignment

  • id

Parameters:
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_block: Iterable[BankedBlockType]
bank: Iterable[Bank]
bank_alignment: BankAlignmentType | None
bank_definition_ref: BankDefinitionRef | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
subspace_map: Iterable[BankedSubspaceType]
usage: UsageType | None
volatile: Volatile | None

org.accellera.ipxact.v1685_2022.banked_block_type module

class org.accellera.ipxact.v1685_2022.banked_block_type.BankedBlockType(name=None, display_name=None, short_description=None, description=None, access_handles=None, range=None, width=None, usage=None, volatile=None, access_policies=None, parameters=None, register=<factory>, register_file=<factory>, vendor_extensions=None, id=None)

Bases: object

Address blocks inside a bank do not specify address.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • range – The address range of an address block. Expressed as the number of addressable units accessible to the block. The range and the width are related by the following formulas: number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range number_of_rows_in_block = number_of_bits_in_block / ipxact:width

  • width – The bit width of a row in the address block. The range and the width are related by the following formulas: number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range number_of_rows_in_block = number_of_bits_in_block / ipxact:width

  • usage – Indicates the usage of this block. Possible values are ‘memory’, ‘register’ and ‘reserved’.

  • volatile

  • access_policies

  • parameters – Any additional parameters needed to describe this address block to the generators.

  • register – A single register

  • register_file – A structure of registers and register files

  • vendor_extensions

  • id

Parameters:
class Register(name=None, display_name=None, short_description=None, description=None, access_handles=None, array=None, address_offset=None, register_definition_ref=None, type_identifier=None, size=None, volatile=None, access_policies=None, field_value=<factory>, alternate_registers=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • array

  • address_offset – Offset from the address block’s baseAddress or the containing register file’s addressOffset, expressed as the number of addressUnitBits from the containing memoryMap or localMemoryMap.

  • register_definition_ref

  • type_identifier – Identifier name used to indicate that multiple register elements contain the exact same information for the elements in the registerDefinitionGroup.

  • size – Width of the register in bits.

  • volatile

  • access_policies

  • field_value – Describes individual bit fields within the register.

  • alternate_registers

  • parameters

  • vendor_extensions

  • id

Parameters:
class RegisterDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_offset: UnsignedLongintExpression | None
alternate_registers: AlternateRegisters | None
array: Array | None
description: Description | None
display_name: DisplayName | None
field_value: Iterable[FieldType]
id: str | None
name: str | None
parameters: Parameters | None
register_definition_ref: RegisterDefinitionRef | None
short_description: ShortDescription | None
size: UnsignedPositiveIntExpression | None
type_identifier: str | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
range: UnsignedPositiveLongintExpression | None
register: Iterable[Register]
register_file: Iterable[RegisterFile]
short_description: ShortDescription | None
usage: UsageType | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
width: UnsignedPositiveIntExpression | None

org.accellera.ipxact.v1685_2022.banked_definition_bank_type module

class org.accellera.ipxact.v1685_2022.banked_definition_bank_type.BankedDefinitionBankType(name=None, display_name=None, short_description=None, description=None, access_handles=None, bank_definition_ref=None, address_block=<factory>, bank=<factory>, usage=None, volatile=None, access_policies=None, parameters=None, bank_alignment=None, id=None)

Bases: object

Banks nested inside a bank do not specify address.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • bank_definition_ref

  • address_block – An address block within the bank. No address information is supplied.

  • bank – A nested bank of blocks within a bank. No address information is supplied.

  • usage – Indicates the usage of this block. Possible values are ‘memory’, ‘register’ and ‘reserved’.

  • volatile

  • access_policies

  • parameters – Any additional parameters needed to describe this address block to the generators.

  • bank_alignment

  • id

Parameters:
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_block: Iterable[BankedBlockType]
bank: Iterable[Bank]
bank_alignment: BankAlignmentType | None
bank_definition_ref: BankDefinitionRef | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
usage: UsageType | None
volatile: Volatile | None

org.accellera.ipxact.v1685_2022.banked_subspace_type module

class org.accellera.ipxact.v1685_2022.banked_subspace_type.BankedSubspaceType(name=None, display_name=None, short_description=None, description=None, parameters=None, vendor_extensions=None, initiator_ref=None, id=None)

Bases: object

Subspace references inside banks do not specify an address.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • parameters – Any parameters that may apply to the subspace reference.

  • vendor_extensions

  • initiator_ref – For subspaceMap elements, this attribute identifies the initiator that contains the address space to be mapped.

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
id: str | None
initiator_ref: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.base_address module

class org.accellera.ipxact.v1685_2022.base_address.BaseAddress(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: UnsignedLongintExpression

Base of an address block, bank or address space.

Expressed as the number of addressable units from the containing memoryMap or localMemoryMap.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.bit_stride module

class org.accellera.ipxact.v1685_2022.bit_stride.BitStride(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[int] = None, maximum: Optional[int] = None, id: Optional[str] = None)

Bases: UnsignedPositiveLongintExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

  • id (str | None)

id: str | None
maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.bits_in_lau module

class org.accellera.ipxact.v1685_2022.bits_in_lau.BitsInLau(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: UnsignedPositiveLongintExpression

The number of bits in the least addressable unit.

The default is byte addressable (8 bits).

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.bus_definition module

class org.accellera.ipxact.v1685_2022.bus_definition.BusDefinition(vendor=None, library=None, name=None, version=None, display_name=None, short_description=None, description=None, direct_connection=None, broadcast=None, is_addressable=None, extends=None, max_initiators=None, max_targets=None, system_group_names=None, choices=None, parameters=None, assertions=None, vendor_extensions=None, id=None)

Bases: object

Defines the structural information associated with a bus type, independent of the abstraction level.

Variables:

  • vendor – Name of the vendor who supplies this file.

  • library – Name of the logical library this element belongs to.

  • name – The name of the object.

  • version – Indicates the version of the named element.

  • display_name – Name for display purposes. Typically a few words providing a more detailed and/or user-friendly name than the vlnv.

  • short_description

  • description

  • direct_connection – This element indicates that a initiator interface may be directly connected to a target interface (under certain conditions) for busses of this type.

  • broadcast – This element indicates that this bus definition supports ‘broadcast’ mode. This means that it is legal to make one-to-many interface connections.

  • is_addressable – If true, indicates that this is an addressable bus.

  • extends – Optional name of bus type that this bus definition is compatible with. This bus definition may change the definitions in the existing bus definition

  • max_initiators – Indicates the maximum number of initiators this bus supports. If this element is not present, the number of initiators allowed is unbounded.

  • max_targets – Indicates the maximum number of targets this bus supports. If the element is not present, the number of targets allowed is unbounded.

  • system_group_names – Indicates the list of system group names that are defined for this bus definition.

  • choices

  • parameters

  • assertions

  • vendor_extensions

  • id

Parameters:
class SystemGroupNames(system_group_name=<factory>)

Bases: object

Variables:

system_group_name – Indicates the name of a system group defined for this bus definition.

Parameters:

system_group_name (Iterable[SystemGroupName])

class SystemGroupName(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
system_group_name: Iterable[SystemGroupName]
assertions: Assertions | None
broadcast: bool | None
choices: Choices | None
description: Description | None
direct_connection: bool | None
display_name: str | None
extends: LibraryRefType | None
id: str | None
is_addressable: bool | None
library: str | None
max_initiators: UnsignedIntExpression | None
max_targets: UnsignedIntExpression | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
system_group_names: SystemGroupNames | None
vendor: str | None
vendor_extensions: VendorExtensions | None
version: str | None

org.accellera.ipxact.v1685_2022.bus_interface module

class org.accellera.ipxact.v1685_2022.bus_interface.BusInterface(name=None, display_name=None, short_description=None, description=None, bus_type=None, abstraction_types=None, initiator=None, target=None, system=None, mirrored_target=None, mirrored_initiator=None, mirrored_system=None, monitor=None, connection_required=None, bits_in_lau=None, bit_steering=None, endianness=None, parameters=None, vendor_extensions=None, id=None, other_attributes=<factory>)

Bases: BusInterfaceType

Describes one of the bus interfaces supported by this component.

Parameters:
class Initiator(address_space_ref=None)

Bases: object

Variables:

address_space_ref – If this initiator connects to an addressable bus, this element references the address space it maps to.

Parameters:

address_space_ref (AddressSpaceRef | None)

class AddressSpaceRef(vendor_extensions=None, address_space_ref=None, id=None, base_address=None, mode_ref=<factory>)

Bases: AddrSpaceRefType

Variables:

  • base_address – Base of an address space.

  • mode_ref

Parameters:
class ModeRef(value='', id=None)

Bases: object

A reference to a mode.

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
address_space_ref: str | None
base_address: SignedLongintExpression | None
id: str | None
mode_ref: Iterable[ModeRef]
vendor_extensions: VendorExtensions | None
address_space_ref: AddressSpaceRef | None
class MirroredSystem(group: org.accellera.ipxact.v1685_2022.group.Group | None = None)

Bases: object

Parameters:

group (Group | None)

group: Group | None
class MirroredTarget(base_addresses=None)

Bases: object

Variables:

base_addresses – Represents a set of remap base addresses.

Parameters:

base_addresses (BaseAddresses | None)

class BaseAddresses(remap_addresses=<factory>, range=None)

Bases: object

Variables:

  • remap_addresses

  • range – The address range of mirrored target, expressed as the number of bitsInLAU from the containing busInterface.

Parameters:
class RemapAddresses(remap_address=None, mode_ref=<factory>, id=None)

Bases: object

Variables:

  • remap_address – Base of an address block, expressed as the number of bitsInLAU from the containing busInterface. The modeRef element indicates the name of the mode for which this address is valid.

  • mode_ref

  • id

Parameters:
id: str | None
mode_ref: Iterable[ModeRef]
remap_address: UnsignedLongintExpression | None
range: UnsignedPositiveLongintExpression | None
remap_addresses: Iterable[RemapAddresses]
base_addresses: BaseAddresses | None
class Monitor(group=None, interface_mode=None)

Bases: object

Variables:

  • group – Indicates which system interface is being monitored. Name must match a group name present on one or more ports in the corresonding bus definition.

  • interface_mode

Parameters:
group: Group | None
interface_mode: MonitorInterfaceMode | None
class System(group: org.accellera.ipxact.v1685_2022.group.Group | None = None)

Bases: object

Parameters:

group (Group | None)

group: Group | None
class Target(memory_map_ref=None, transparent_bridge=<factory>, file_set_ref_group=<factory>)

Bases: object

Variables:

  • memory_map_ref

  • transparent_bridge

  • file_set_ref_group – This reference is used to point the filesets that are associated with this target port. Depending on the target port function, there may be completely different software drivers associated with the different ports.

Parameters:
class FileSetRefGroup(group=None, file_set_ref=<factory>, id=None)

Bases: object

Variables:

  • group – Abritray name assigned to the collections of fileSets.

  • file_set_ref

  • id

Parameters:

  • group (str | None)

  • file_set_ref (Iterable[FileSetRef])

  • id (str | None)

file_set_ref: Iterable[FileSetRef]
group: str | None
id: str | None
file_set_ref_group: Iterable[FileSetRefGroup]
memory_map_ref: MemoryMapRef | None
transparent_bridge: Iterable[TransparentBridge]
abstraction_types: AbstractionTypes | None
bit_steering: UnsignedBitExpression | None
bits_in_lau: BitsInLau | None
bus_type: ConfigurableLibraryRefType | None
connection_required: bool | None
description: Description | None
display_name: DisplayName | None
endianness: EndianessType | None
id: str | None
initiator: 'BusInterfaceType.Initiator' | None
mirrored_initiator: object | None
mirrored_system: 'BusInterfaceType.MirroredSystem' | None
mirrored_target: 'BusInterfaceType.MirroredTarget' | None
monitor: 'BusInterfaceType.Monitor' | None
name: str | None
other_attributes: Mapping[str, str]
parameters: Parameters | None
short_description: ShortDescription | None
system: 'BusInterfaceType.System' | None
target: 'BusInterfaceType.Target' | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.bus_interface_type module

class org.accellera.ipxact.v1685_2022.bus_interface_type.BusInterfaceType(name=None, display_name=None, short_description=None, description=None, bus_type=None, abstraction_types=None, initiator=None, target=None, system=None, mirrored_target=None, mirrored_initiator=None, mirrored_system=None, monitor=None, connection_required=None, bits_in_lau=None, bit_steering=None, endianness=None, parameters=None, vendor_extensions=None, id=None, other_attributes=<factory>)

Bases: object

Type definition for a busInterface in a component.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • bus_type – The bus type of this interface. Refers to bus definition using vendor, library, name, version attributes along with any configurable element values needed to configure this interface.

  • abstraction_types

  • initiator – If this element is present, the bus interface can serve as a initiator. This element encapsulates additional information related to its role as initiator.

  • target – If this element is present, the bus interface can serve as a target.

  • system – If this element is present, the bus interface is a system interface, neither initiator nor target, with a specific function on the bus.

  • mirrored_target – If this element is present, the bus interface represents a mirrored target interface. All directional constraints on ports are reversed relative to the specification in the bus definition.

  • mirrored_initiator – If this element is present, the bus interface represents a mirrored initiator interface. All directional constraints on ports are reversed relative to the specification in the bus definition.

  • mirrored_system – If this element is present, the bus interface represents a mirrored system interface. All directional constraints on ports are reversed relative to the specification in the bus definition.

  • monitor – Indicates that this is a (passive) monitor interface. All of the ports in the interface must be inputs. The type of interface to be monitored is specified with the required interfaceType attribute. The ipxact:group element must be specified if monitoring a system interface.

  • connection_required – Indicates whether a connection to this interface is required for proper component functionality.

  • bits_in_lau

  • bit_steering – Indicates whether bit steering should be used to map this interface onto a bus of different data width. Values are “0”, “1” (defaults to “0”).

  • endianness – ‘big’: means the most significant element of any multi-element data field is stored at the lowest memory address. ‘little’ means the least significant element of any multi-element data field is stored at the lowest memory address. If this element is not present the default is ‘little’ endian.

  • parameters

  • vendor_extensions

  • id

  • other_attributes

Parameters:
class Initiator(address_space_ref=None)

Bases: object

Variables:

address_space_ref – If this initiator connects to an addressable bus, this element references the address space it maps to.

Parameters:

address_space_ref (AddressSpaceRef | None)

class AddressSpaceRef(vendor_extensions=None, address_space_ref=None, id=None, base_address=None, mode_ref=<factory>)

Bases: AddrSpaceRefType

Variables:

  • base_address – Base of an address space.

  • mode_ref

Parameters:
class ModeRef(value='', id=None)

Bases: object

A reference to a mode.

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
address_space_ref: str | None
base_address: SignedLongintExpression | None
id: str | None
mode_ref: Iterable[ModeRef]
vendor_extensions: VendorExtensions | None
address_space_ref: AddressSpaceRef | None
class MirroredSystem(group: org.accellera.ipxact.v1685_2022.group.Group | None = None)

Bases: object

Parameters:

group (Group | None)

group: Group | None
class MirroredTarget(base_addresses=None)

Bases: object

Variables:

base_addresses – Represents a set of remap base addresses.

Parameters:

base_addresses (BaseAddresses | None)

class BaseAddresses(remap_addresses=<factory>, range=None)

Bases: object

Variables:

  • remap_addresses

  • range – The address range of mirrored target, expressed as the number of bitsInLAU from the containing busInterface.

Parameters:
class RemapAddresses(remap_address=None, mode_ref=<factory>, id=None)

Bases: object

Variables:

  • remap_address – Base of an address block, expressed as the number of bitsInLAU from the containing busInterface. The modeRef element indicates the name of the mode for which this address is valid.

  • mode_ref

  • id

Parameters:
id: str | None
mode_ref: Iterable[ModeRef]
remap_address: UnsignedLongintExpression | None
range: UnsignedPositiveLongintExpression | None
remap_addresses: Iterable[RemapAddresses]
base_addresses: BaseAddresses | None
class Monitor(group=None, interface_mode=None)

Bases: object

Variables:

  • group – Indicates which system interface is being monitored. Name must match a group name present on one or more ports in the corresonding bus definition.

  • interface_mode

Parameters:
group: Group | None
interface_mode: MonitorInterfaceMode | None
class System(group: org.accellera.ipxact.v1685_2022.group.Group | None = None)

Bases: object

Parameters:

group (Group | None)

group: Group | None
class Target(memory_map_ref=None, transparent_bridge=<factory>, file_set_ref_group=<factory>)

Bases: object

Variables:

  • memory_map_ref

  • transparent_bridge

  • file_set_ref_group – This reference is used to point the filesets that are associated with this target port. Depending on the target port function, there may be completely different software drivers associated with the different ports.

Parameters:
class FileSetRefGroup(group=None, file_set_ref=<factory>, id=None)

Bases: object

Variables:

  • group – Abritray name assigned to the collections of fileSets.

  • file_set_ref

  • id

Parameters:

  • group (str | None)

  • file_set_ref (Iterable[FileSetRef])

  • id (str | None)

file_set_ref: Iterable[FileSetRef]
group: str | None
id: str | None
file_set_ref_group: Iterable[FileSetRefGroup]
memory_map_ref: MemoryMapRef | None
transparent_bridge: Iterable[TransparentBridge]
abstraction_types: AbstractionTypes | None
bit_steering: UnsignedBitExpression | None
bits_in_lau: BitsInLau | None
bus_type: ConfigurableLibraryRefType | None
connection_required: bool | None
description: Description | None
display_name: DisplayName | None
endianness: EndianessType | None
id: str | None
initiator: Initiator | None
mirrored_initiator: object | None
mirrored_system: MirroredSystem | None
mirrored_target: MirroredTarget | None
monitor: Monitor | None
name: str | None
other_attributes: Mapping[str, str]
parameters: Parameters | None
short_description: ShortDescription | None
system: System | None
target: Target | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.bus_interfaces module

class org.accellera.ipxact.v1685_2022.bus_interfaces.BusInterfaces(bus_interface=<factory>)

Bases: object

A list of bus interfaces supported by this component.

Parameters:

bus_interface (Iterable[BusInterface])

bus_interface: Iterable[BusInterface]

org.accellera.ipxact.v1685_2022.bus_width module

class org.accellera.ipxact.v1685_2022.bus_width.BusWidth(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: UnsignedIntExpression

Defines the bus size in bits.

This can be the result of an expression.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.catalog module

class org.accellera.ipxact.v1685_2022.catalog.Catalog(vendor=None, library=None, name=None, version=None, display_name=None, short_description=None, description=None, catalogs=None, bus_definitions=None, abstraction_definitions=None, components=None, abstractors=None, designs=None, design_configurations=None, generator_chains=None, type_definitions=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • vendor – Name of the vendor who supplies this file.

  • library – Name of the logical library this element belongs to.

  • name – The name of the object.

  • version – Indicates the version of the named element.

  • display_name – Name for display purposes. Typically a few words providing a more detailed and/or user-friendly name than the vlnv.

  • short_description

  • description

  • catalogs

  • bus_definitions

  • abstraction_definitions

  • components

  • abstractors

  • designs

  • design_configurations

  • generator_chains

  • type_definitions

  • vendor_extensions

  • id

Parameters:
abstraction_definitions: IpxactFilesType | None
abstractors: IpxactFilesType | None
bus_definitions: IpxactFilesType | None
catalogs: IpxactFilesType | None
components: IpxactFilesType | None
description: Description | None
design_configurations: IpxactFilesType | None
designs: IpxactFilesType | None
display_name: str | None
generator_chains: IpxactFilesType | None
id: str | None
library: str | None
name: str | None
short_description: ShortDescription | None
type_definitions: IpxactFilesType | None
vendor: str | None
vendor_extensions: VendorExtensions | None
version: str | None

org.accellera.ipxact.v1685_2022.cell_class_value_type module

class org.accellera.ipxact.v1685_2022.cell_class_value_type.CellClassValueType(*values)

Bases: Enum

Indicates legal cell class values.

COMBINATIONAL = 'combinational'
SEQUENTIAL = 'sequential'

org.accellera.ipxact.v1685_2022.cell_function_value_type module

class org.accellera.ipxact.v1685_2022.cell_function_value_type.CellFunctionValueType(*values)

Bases: Enum

Indicates legal cell function values.

BUF = 'buf'
DFF = 'dff'
INV = 'inv'
LATCH = 'latch'
MUX21 = 'mux21'
NAND2 = 'nand2'
OTHER = 'other'
XOR2 = 'xor2'

org.accellera.ipxact.v1685_2022.cell_specification module

class org.accellera.ipxact.v1685_2022.cell_specification.CellSpecification(cell_function=None, cell_class=None, cell_strength=None)

Bases: object

Used to provide a generic description of a technology library cell.

Variables:

  • cell_function – Defines a technology library cell in library independent fashion, based on specification of a cell function and strength.

  • cell_class – Defines a technology library cell in library independent fashion, based on specification of a cell class and strength.

  • cell_strength – Indicates the desired strength of the specified cell.

Parameters:
class CellFunction(value: org.accellera.ipxact.v1685_2022.cell_function_value_type.CellFunctionValueType | None = None, other: str | None = None)

Bases: object

Parameters:
other: str | None
value: CellFunctionValueType | None
cell_class: CellClassValueType | None
cell_function: CellFunction | None
cell_strength: CellStrengthValueType | None

org.accellera.ipxact.v1685_2022.cell_strength_value_type module

class org.accellera.ipxact.v1685_2022.cell_strength_value_type.CellStrengthValueType(*values)

Bases: Enum

Indicates legal cell strength values.

HIGH = 'high'
LOW = 'low'
MEDIAN = 'median'

org.accellera.ipxact.v1685_2022.channels module

class org.accellera.ipxact.v1685_2022.channels.Channels(channel=<factory>)

Bases: object

Lists all channel connections between mirror interfaces of this component.

Variables:

channel – Defines a set of mirrored interfaces of this component that are connected to one another.

Parameters:

channel (Iterable[Channel])

class Channel(name=None, display_name=None, short_description=None, description=None, bus_interface_ref=<factory>, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • bus_interface_ref – Contains the name of one of the bus interfaces that is part of this channel. The ordering of the references may be important to the design environment.

  • vendor_extensions

  • id

Parameters:
class BusInterfaceRef(local_name: str | None = None, vendor_extensions: org.accellera.ipxact.v1685_2022.vendor_extensions.VendorExtensions | None = None, id: str | None = None)

Bases: object

Parameters:

  • local_name (str | None)

  • vendor_extensions (VendorExtensions | None)

  • id (str | None)

id: str | None
local_name: str | None
vendor_extensions: VendorExtensions | None
bus_interface_ref: Iterable[BusInterfaceRef]
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
channel: Iterable[Channel]

org.accellera.ipxact.v1685_2022.choices module

class org.accellera.ipxact.v1685_2022.choices.Choices(choice=<factory>)

Bases: object

Choices used by elements with an attribute ipxact:choiceRef.

Variables:

choice – Non-empty set of legal values for a elements with an attribute ipxact:choiceRef.

Parameters:

choice (Iterable[Choice])

class Choice(name=None, enumeration=<factory>, id=None)

Bases: object

Variables:

  • name – Choice key, available for reference by the ipxact:choiceRef attribute.

  • enumeration – One possible value of ipxact:choice

  • id

Parameters:

  • name (str | None)

  • enumeration (Iterable[Enumeration])

  • id (str | None)

class Enumeration(value='', other_attributes=<factory>, text=None, help=None, id=None)

Bases: ComplexBaseExpression

Variables:

  • text – When specified, displayed in place of the ipxact:enumeration value

  • help – Text that may be displayed if the user requests help about the meaning of an element

  • id

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • text (str | None)

  • help (str | None)

  • id (str | None)

help: str | None
id: str | None
other_attributes: Mapping[str, str]
text: str | None
value: str
enumeration: Iterable[Enumeration]
id: str | None
name: str | None
choice: Iterable[Choice]

org.accellera.ipxact.v1685_2022.clearbox_element_ref_type module

class org.accellera.ipxact.v1685_2022.clearbox_element_ref_type.ClearboxElementRefType(location=<factory>, vendor_extensions=None, name=None, id=None)

Bases: object

Reference to a clearboxElement within a view.

The ‘name’ attribute must refer to a clearboxElement defined within this component.

Variables:

  • location – The contents of each location element can be used to specified one location (HDL Path) through the referenced clearBoxElement is accessible.

  • vendor_extensions

  • name – Reference to a clearboxElement defined within this component.

  • id

Parameters:
id: str | None
location: Iterable[SlicesType]
name: str | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.clearbox_element_type module

class org.accellera.ipxact.v1685_2022.clearbox_element_type.ClearboxElementType(name=None, display_name=None, short_description=None, description=None, clearbox_type=None, driveable=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Defines a clear box reference point within the component.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • clearbox_type – Indicates the type of the element. The pin and signal types refer to elements within the HDL description. The interface type refers to a group of signals addressed as a single unit.

  • driveable – If true, indicates that the clear box element can be driven (e.g. have a new value forced into it).

  • parameters

  • vendor_extensions

  • id

Parameters:
clearbox_type: SimpleClearboxType | None
description: Description | None
display_name: DisplayName | None
driveable: bool | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.clock_driver module

class org.accellera.ipxact.v1685_2022.clock_driver.ClockDriver(clock_period=None, clock_pulse_offset=None, clock_pulse_value=None, clock_pulse_duration=None, id=None, clock_name=None)

Bases: ClockDriverType

Describes a driven clock port.

Variables:

clock_name – Indicates the name of the cllock. If not specified the name is assumed to be the name of the containing port.

Parameters:
class ClockPeriod(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[float] = None, maximum: Optional[float] = None, units: org.accellera.ipxact.v1685_2022.delay_value_unit_type.DelayValueUnitType = <DelayValueUnitType.NS: 'ns'>)

Bases: RealExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

  • units (DelayValueUnitType)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
units: DelayValueUnitType
value: str
class ClockPulseDuration(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[float] = None, maximum: Optional[float] = None, units: org.accellera.ipxact.v1685_2022.delay_value_unit_type.DelayValueUnitType = <DelayValueUnitType.NS: 'ns'>)

Bases: RealExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

  • units (DelayValueUnitType)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
units: DelayValueUnitType
value: str
class ClockPulseOffset(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[float] = None, maximum: Optional[float] = None, units: org.accellera.ipxact.v1685_2022.delay_value_unit_type.DelayValueUnitType = <DelayValueUnitType.NS: 'ns'>)

Bases: RealExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

  • units (DelayValueUnitType)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
units: DelayValueUnitType
value: str
clock_name: str | None
clock_period: 'ClockDriverType.ClockPeriod' | None
clock_pulse_duration: 'ClockDriverType.ClockPulseDuration' | None
clock_pulse_offset: 'ClockDriverType.ClockPulseOffset' | None
clock_pulse_value: UnsignedBitExpression | None
id: str | None

org.accellera.ipxact.v1685_2022.clock_driver_type module

class org.accellera.ipxact.v1685_2022.clock_driver_type.ClockDriverType(clock_period=None, clock_pulse_offset=None, clock_pulse_value=None, clock_pulse_duration=None, id=None)

Bases: object

Variables:

  • clock_period – Clock period in units defined by the units attribute. Default is nanoseconds.

  • clock_pulse_offset – Time until first pulse. Units are defined by the units attribute. Default is nanoseconds.

  • clock_pulse_value – Value of port after first clock edge.

  • clock_pulse_duration – Duration of first state in cycle. Units are defined by the units attribute. Default is nanoseconds.

  • id

Parameters:
class ClockPeriod(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[float] = None, maximum: Optional[float] = None, units: org.accellera.ipxact.v1685_2022.delay_value_unit_type.DelayValueUnitType = <DelayValueUnitType.NS: 'ns'>)

Bases: RealExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

  • units (DelayValueUnitType)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
units: DelayValueUnitType
value: str
class ClockPulseDuration(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[float] = None, maximum: Optional[float] = None, units: org.accellera.ipxact.v1685_2022.delay_value_unit_type.DelayValueUnitType = <DelayValueUnitType.NS: 'ns'>)

Bases: RealExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

  • units (DelayValueUnitType)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
units: DelayValueUnitType
value: str
class ClockPulseOffset(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[float] = None, maximum: Optional[float] = None, units: org.accellera.ipxact.v1685_2022.delay_value_unit_type.DelayValueUnitType = <DelayValueUnitType.NS: 'ns'>)

Bases: RealExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

  • units (DelayValueUnitType)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
units: DelayValueUnitType
value: str
clock_period: ClockPeriod | None
clock_pulse_duration: ClockPulseDuration | None
clock_pulse_offset: ClockPulseOffset | None
clock_pulse_value: UnsignedBitExpression | None
id: str | None

org.accellera.ipxact.v1685_2022.complex_base_expression module

class org.accellera.ipxact.v1685_2022.complex_base_expression.ComplexBaseExpression(value='', other_attributes=<factory>)

Bases: object

Represents the base-type for an expressions.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.complex_tied_value_expression module

class org.accellera.ipxact.v1685_2022.complex_tied_value_expression.ComplexTiedValueExpression(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: object

An unsigned bit vector expression that resolves to the value set {0, 1, …} or or the string values ‘open’ or ‘default’.

It is derived from simpleUnsignedBitVectorExpression and it supports an expression value.

Variables:

  • value

  • other_attributes

  • minimum – For elements which can be specified using expression which are supposed to be resolved to a long value, this indicates the minimum value allowed.

  • maximum – For elements which can be specified using expression which are supposed to be resolved to a long value, this indicates the maximum value allowed.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.component module

class org.accellera.ipxact.v1685_2022.component.Component(vendor=None, library=None, name=None, version=None, display_name=None, short_description=None, description=None, type_definitions=None, power_domains=None, bus_interfaces=None, indirect_interfaces=None, channels=None, modes=None, address_spaces=None, memory_maps=None, model=None, component_generators=None, choices=None, file_sets=None, clearbox_elements=None, cpus=None, other_clock_drivers=None, reset_types=None, parameters=None, assertions=None, vendor_extensions=None, id=None)

Bases: ComponentType

This is the root element for all non platform-core components.

Parameters:
class ClearboxElements(clearbox_element=<factory>)

Bases: object

Variables:

clearbox_element – A clearboxElement is a useful way to identify elements of a component that can not be identified through other means such as internal signals and non- software accessible registers.

Parameters:

clearbox_element (Iterable[ClearboxElementType])

clearbox_element: Iterable[ClearboxElementType]
class Cpus(cpu=<factory>)

Bases: object

Variables:

cpu – Describes a processor in this component.

Parameters:

cpu (Iterable[Cpu])

class Cpu(name=None, display_name=None, short_description=None, description=None, range=None, width=None, regions=None, address_unit_bits=None, executable_image=<factory>, memory_map_ref=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • range – The address range of an address block. Expressed as the number of addressable units accessible to the block. The range and the width are related by the following formulas: number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range number_of_rows_in_block = number_of_bits_in_block / ipxact:width

  • width – The bit width of a row in the address block. The range and the width are related by the following formulas: number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range number_of_rows_in_block = number_of_bits_in_block / ipxact:width

  • regions – Address regions within a cpu system address map.

  • address_unit_bits

  • executable_image

  • memory_map_ref – Indicates which memory maps into this cpu.

  • parameters – Data specific to the cpu.

  • vendor_extensions

  • id

Parameters:
class Regions(region=<factory>)

Bases: object

Variables:

region – Address region within a system address map.

Parameters:

region (Iterable[Region])

class Region(name=None, display_name=None, short_description=None, description=None, address_offset=None, range=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • address_offset – Address offset of the region within the system address map.

  • range – The address range of region. Expressed as the number of addressable units accessible to the region.

  • vendor_extensions

  • id

Parameters:
address_offset: UnsignedLongintExpression | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
range: UnsignedPositiveLongintExpression | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
region: Iterable[Region]
address_unit_bits: AddressUnitBits | None
description: Description | None
display_name: DisplayName | None
executable_image: Iterable[ExecutableImage]
id: str | None
memory_map_ref: str | None
name: str | None
parameters: Parameters | None
range: UnsignedPositiveLongintExpression | None
regions: Regions | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
width: UnsignedPositiveIntExpression | None
cpu: Iterable[Cpu]
class Modes(mode: collections.abc.Iterable['ComponentType.Modes.Mode'] = <factory>)

Bases: object

Parameters:

mode (Iterable[Mode])

class Mode(name=None, display_name=None, short_description=None, description=None, port_slice=<factory>, field_slice=<factory>, condition=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • port_slice

  • field_slice – Reference to a register field slice

  • condition

  • vendor_extensions

  • id

Parameters:
class FieldSlice(name=None, display_name=None, short_description=None, description=None, address_space_ref=None, memory_map_ref=None, memory_remap_ref=None, bank_ref=<factory>, address_block_ref=None, register_file_ref=<factory>, register_ref=None, alternate_register_ref=None, field_ref=None, range=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • address_space_ref

  • memory_map_ref

  • memory_remap_ref

  • bank_ref

  • address_block_ref

  • register_file_ref

  • register_ref

  • alternate_register_ref

  • field_ref

  • range

  • id

Parameters:
class AddressSpaceRef(address_space_ref: str | None = None)

Bases: object

Parameters:

address_space_ref (str | None)

address_space_ref: str | None
class MemoryMapRef(memory_map_ref: str | None = None)

Bases: object

Parameters:

memory_map_ref (str | None)

memory_map_ref: str | None
address_block_ref: AddressBlockRef | None
address_space_ref: AddressSpaceRef | None
alternate_register_ref: AlternateRegisterRef | None
bank_ref: Iterable[BankRef]
description: Description | None
display_name: DisplayName | None
field_ref: FieldRef | None
id: str | None
memory_map_ref: MemoryMapRef | None
memory_remap_ref: MemoryRemapRef | None
name: str | None
range: Range | None
register_file_ref: Iterable[RegisterFileRef]
register_ref: RegisterRef | None
short_description: ShortDescription | None
class PortSlice(name=None, display_name=None, short_description=None, description=None, port_ref=None, sub_port_reference=<factory>, part_select=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • port_ref

  • sub_port_reference

  • part_select

  • id

Parameters:
class PortRef(port_ref: str | None = None)

Bases: object

Parameters:

port_ref (str | None)

port_ref: str | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
part_select: PartSelect | None
port_ref: PortRef | None
short_description: ShortDescription | None
sub_port_reference: Iterable[SubPortReference]
condition: UnresolvedUnsignedBitExpression | None
description: Description | None
display_name: DisplayName | None
field_slice: Iterable[FieldSlice]
id: str | None
name: str | None
port_slice: Iterable[PortSlice]
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
mode: Iterable[Mode]
class PowerDomains(power_domain: collections.abc.Iterable['ComponentType.PowerDomains.PowerDomain'] = <factory>)

Bases: object

Parameters:

power_domain (Iterable[PowerDomain])

class PowerDomain(name=None, display_name=None, short_description=None, description=None, always_on=None, sub_domain_of=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • always_on

  • sub_domain_of – Reference to a power domain defined on this component

  • parameters

  • vendor_extensions

  • id

Parameters:
always_on: AlwaysOn | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
sub_domain_of: str | None
vendor_extensions: VendorExtensions | None
power_domain: Iterable[PowerDomain]
class ResetTypes(reset_type=<factory>)

Bases: object

Variables:

reset_type – A user defined reset policy

Parameters:

reset_type (Iterable[ResetType])

class ResetType(name=None, display_name=None, short_description=None, description=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • vendor_extensions

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
reset_type: Iterable[ResetType]
class TypeDefinitions(external_type_definitions: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.external_type_definitions.ExternalTypeDefinitions] = <factory>)

Bases: object

Parameters:

external_type_definitions (Iterable[ExternalTypeDefinitions])

external_type_definitions: Iterable[ExternalTypeDefinitions]
address_spaces: AddressSpaces | None
assertions: Assertions | None
bus_interfaces: BusInterfaces | None
channels: Channels | None
choices: Choices | None
clearbox_elements: 'ComponentType.ClearboxElements' | None
component_generators: ComponentGenerators | None
cpus: 'ComponentType.Cpus' | None
description: Description | None
display_name: str | None
file_sets: FileSets | None
id: str | None
indirect_interfaces: IndirectInterfaces | None
library: str | None
memory_maps: MemoryMaps | None
model: Model | None
modes: 'ComponentType.Modes' | None
name: str | None
other_clock_drivers: OtherClocks | None
parameters: Parameters | None
power_domains: 'ComponentType.PowerDomains' | None
reset_types: 'ComponentType.ResetTypes' | None
short_description: ShortDescription | None
type_definitions: 'ComponentType.TypeDefinitions' | None
vendor: str | None
vendor_extensions: VendorExtensions | None
version: str | None

org.accellera.ipxact.v1685_2022.component_generator module

class org.accellera.ipxact.v1685_2022.component_generator.ComponentGenerator(name=None, display_name=None, short_description=None, description=None, phase=None, parameters=None, api_type=None, api_service=None, transport_methods=None, generator_exe=None, vendor_extensions=None, hidden=False, id=None, group=<factory>, scope=InstanceGeneratorTypeScope.INSTANCE)

Bases: InstanceGeneratorType

Specifies a set of component generators.

The scope attribute applies to component generators and specifies whether the generator should be run for each instance of the entity (or module) or just once for all instances of the entity.

Parameters:
api_service: GeneratorTypeApiService | None
api_type: 'GeneratorType.ApiType' | None
description: Description | None
display_name: DisplayName | None
generator_exe: IpxactUri | None
group: Iterable['InstanceGeneratorType.Group']
hidden: bool
id: str | None
name: str | None
parameters: Parameters | None
phase: Phase | None
scope: InstanceGeneratorTypeScope
short_description: ShortDescription | None
transport_methods: 'GeneratorType.TransportMethods' | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.component_generators module

class org.accellera.ipxact.v1685_2022.component_generators.ComponentGenerators(component_generator=<factory>)

Bases: object

List of component generators.

Parameters:

component_generator (Iterable[ComponentGenerator])

component_generator: Iterable[ComponentGenerator]

org.accellera.ipxact.v1685_2022.component_instance module

class org.accellera.ipxact.v1685_2022.component_instance.ComponentInstance(instance_name=None, display_name=None, short_description=None, description=None, component_ref=None, power_domain_links=None, vendor_extensions=None, id=None)

Bases: object

Component instance element.

The instance name is contained in the unique-value instanceName attribute.

Variables:

  • instance_name

  • display_name

  • short_description

  • description

  • component_ref – References a component to be found in an external library. The four attributes define the VLNV of the referenced element.

  • power_domain_links

  • vendor_extensions

  • id

Parameters:
component_ref: ConfigurableLibraryRefType | None
description: Description | None
display_name: DisplayName | None
id: str | None
instance_name: InstanceName | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.component_instances module

class org.accellera.ipxact.v1685_2022.component_instances.ComponentInstances(component_instance=<factory>)

Bases: object

Sub instances of internal components.

Parameters:

component_instance (Iterable[ComponentInstance])

component_instance: Iterable[ComponentInstance]

org.accellera.ipxact.v1685_2022.component_instantiation_type module

class org.accellera.ipxact.v1685_2022.component_instantiation_type.ComponentInstantiationType(name=None, display_name=None, short_description=None, description=None, is_virtual=None, language=None, library_name=None, package_name=None, module_name=None, architecture_name=None, configuration_name=None, module_parameters=None, default_file_builder=<factory>, file_set_ref=<factory>, constraint_set_ref=<factory>, clearbox_element_refs=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Component instantiation type.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • is_virtual – When true, indicates that this component should not be netlisted.

  • language – The hardware description language used such as “verilog” or “vhdl”. If the attribute “strict” is “true”, this value must match the language being generated for the design.

  • library_name – A string specifying the library name in which the model should be compiled. If the libraryName element is not present then its value defaults to “work”.

  • package_name – A string describing the VHDL package containing the interface of the model. If the packageName element is not present then its value defaults to the component VLNV name concatenated with postfix “_cmp_pkg” which stands for component package.

  • module_name – A string describing the Verilog, SystemVerilog, or SystemC module name or the VHDL entity name. If the moduleName is not present then its value defaults to the component VLNV name

  • architecture_name – A string describing the VHDL architecture name. If the architectureName element is not present then its value defaults to “rtl”.

  • configuration_name – A string describing the Verilog, SystemVerilog, or VHDL configuration name. If the configurationName element is not present then its value defaults to the design configuration VLNV name of the design configuration associated with the active hierarchical view or, if there is no active hierarchical view, to the component VLNV name concatenated with postfix “_rtl_cfg”.

  • module_parameters – Model parameter name value pairs container

  • default_file_builder – Default command and flags used to build derived files from the sourceName files in the referenced file sets.

  • file_set_ref

  • constraint_set_ref

  • clearbox_element_refs – Container for clear box element references.

  • parameters

  • vendor_extensions

  • id

Parameters:
class ClearboxElementRefs(clearbox_element_ref=<factory>)

Bases: object

Variables:

clearbox_element_ref – Reference to a clear box element which is visible within this view.

Parameters:

clearbox_element_ref (Iterable[ClearboxElementRefType])

clearbox_element_ref: Iterable[ClearboxElementRefType]
class ModuleParameters(module_parameter=<factory>)

Bases: object

Variables:

module_parameter – A module parameter name value pair. The name is given in an attribute. The value is the element value. The dataType (applicable to high level modeling) is given in the dataType attribute. For hardware based models, the name should be identical to the RTL (VHDL generic or Verilog parameter). The usageType attribute indicates how the model parameter is to be used.

Parameters:

module_parameter (Iterable[ModuleParameterType])

module_parameter: Iterable[ModuleParameterType]
architecture_name: str | None
clearbox_element_refs: ClearboxElementRefs | None
configuration_name: str | None
constraint_set_ref: Iterable[ConstraintSetRef]
default_file_builder: Iterable[FileBuilderType]
description: Description | None
display_name: DisplayName | None
file_set_ref: Iterable[FileSetRef]
id: str | None
is_virtual: bool | None
language: LanguageType | None
library_name: str | None
module_name: str | None
module_parameters: ModuleParameters | None
name: str | None
package_name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.component_port_direction_type module

class org.accellera.ipxact.v1685_2022.component_port_direction_type.ComponentPortDirectionType(*values)

Bases: Enum

The direction of a component port.

IN = 'in'
INOUT = 'inout'
OUT = 'out'
PHANTOM = 'phantom'

org.accellera.ipxact.v1685_2022.component_type module

class org.accellera.ipxact.v1685_2022.component_type.ComponentType(vendor=None, library=None, name=None, version=None, display_name=None, short_description=None, description=None, type_definitions=None, power_domains=None, bus_interfaces=None, indirect_interfaces=None, channels=None, modes=None, address_spaces=None, memory_maps=None, model=None, component_generators=None, choices=None, file_sets=None, clearbox_elements=None, cpus=None, other_clock_drivers=None, reset_types=None, parameters=None, assertions=None, vendor_extensions=None, id=None)

Bases: object

Component-specific extension to componentType.

Variables:

  • vendor – Name of the vendor who supplies this file.

  • library – Name of the logical library this element belongs to.

  • name – The name of the object.

  • version – Indicates the version of the named element.

  • display_name – Name for display purposes. Typically a few words providing a more detailed and/or user-friendly name than the vlnv.

  • short_description

  • description

  • type_definitions

  • power_domains

  • bus_interfaces

  • indirect_interfaces

  • channels

  • modes – A list of user defined component modes.

  • address_spaces

  • memory_maps

  • model

  • component_generators – Generator list is tools-specific.

  • choices

  • file_sets

  • clearbox_elements – A list of clearboxElements

  • cpus – cpu’s in the component

  • other_clock_drivers – Defines a set of clock drivers that are not directly associated with an input port of the component.

  • reset_types – A list of user defined resetTypes applicable to this component.

  • parameters

  • assertions

  • vendor_extensions

  • id

Parameters:
class ClearboxElements(clearbox_element=<factory>)

Bases: object

Variables:

clearbox_element – A clearboxElement is a useful way to identify elements of a component that can not be identified through other means such as internal signals and non- software accessible registers.

Parameters:

clearbox_element (Iterable[ClearboxElementType])

clearbox_element: Iterable[ClearboxElementType]
class Cpus(cpu=<factory>)

Bases: object

Variables:

cpu – Describes a processor in this component.

Parameters:

cpu (Iterable[Cpu])

class Cpu(name=None, display_name=None, short_description=None, description=None, range=None, width=None, regions=None, address_unit_bits=None, executable_image=<factory>, memory_map_ref=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • range – The address range of an address block. Expressed as the number of addressable units accessible to the block. The range and the width are related by the following formulas: number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range number_of_rows_in_block = number_of_bits_in_block / ipxact:width

  • width – The bit width of a row in the address block. The range and the width are related by the following formulas: number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range number_of_rows_in_block = number_of_bits_in_block / ipxact:width

  • regions – Address regions within a cpu system address map.

  • address_unit_bits

  • executable_image

  • memory_map_ref – Indicates which memory maps into this cpu.

  • parameters – Data specific to the cpu.

  • vendor_extensions

  • id

Parameters:
class Regions(region=<factory>)

Bases: object

Variables:

region – Address region within a system address map.

Parameters:

region (Iterable[Region])

class Region(name=None, display_name=None, short_description=None, description=None, address_offset=None, range=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • address_offset – Address offset of the region within the system address map.

  • range – The address range of region. Expressed as the number of addressable units accessible to the region.

  • vendor_extensions

  • id

Parameters:
address_offset: UnsignedLongintExpression | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
range: UnsignedPositiveLongintExpression | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
region: Iterable[Region]
address_unit_bits: AddressUnitBits | None
description: Description | None
display_name: DisplayName | None
executable_image: Iterable[ExecutableImage]
id: str | None
memory_map_ref: str | None
name: str | None
parameters: Parameters | None
range: UnsignedPositiveLongintExpression | None
regions: Regions | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
width: UnsignedPositiveIntExpression | None
cpu: Iterable[Cpu]
class Modes(mode: collections.abc.Iterable['ComponentType.Modes.Mode'] = <factory>)

Bases: object

Parameters:

mode (Iterable[Mode])

class Mode(name=None, display_name=None, short_description=None, description=None, port_slice=<factory>, field_slice=<factory>, condition=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • port_slice

  • field_slice – Reference to a register field slice

  • condition

  • vendor_extensions

  • id

Parameters:
class FieldSlice(name=None, display_name=None, short_description=None, description=None, address_space_ref=None, memory_map_ref=None, memory_remap_ref=None, bank_ref=<factory>, address_block_ref=None, register_file_ref=<factory>, register_ref=None, alternate_register_ref=None, field_ref=None, range=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • address_space_ref

  • memory_map_ref

  • memory_remap_ref

  • bank_ref

  • address_block_ref

  • register_file_ref

  • register_ref

  • alternate_register_ref

  • field_ref

  • range

  • id

Parameters:
class AddressSpaceRef(address_space_ref: str | None = None)

Bases: object

Parameters:

address_space_ref (str | None)

address_space_ref: str | None
class MemoryMapRef(memory_map_ref: str | None = None)

Bases: object

Parameters:

memory_map_ref (str | None)

memory_map_ref: str | None
address_block_ref: AddressBlockRef | None
address_space_ref: AddressSpaceRef | None
alternate_register_ref: AlternateRegisterRef | None
bank_ref: Iterable[BankRef]
description: Description | None
display_name: DisplayName | None
field_ref: FieldRef | None
id: str | None
memory_map_ref: MemoryMapRef | None
memory_remap_ref: MemoryRemapRef | None
name: str | None
range: Range | None
register_file_ref: Iterable[RegisterFileRef]
register_ref: RegisterRef | None
short_description: ShortDescription | None
class PortSlice(name=None, display_name=None, short_description=None, description=None, port_ref=None, sub_port_reference=<factory>, part_select=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • port_ref

  • sub_port_reference

  • part_select

  • id

Parameters:
class PortRef(port_ref: str | None = None)

Bases: object

Parameters:

port_ref (str | None)

port_ref: str | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
part_select: PartSelect | None
port_ref: PortRef | None
short_description: ShortDescription | None
sub_port_reference: Iterable[SubPortReference]
condition: UnresolvedUnsignedBitExpression | None
description: Description | None
display_name: DisplayName | None
field_slice: Iterable[FieldSlice]
id: str | None
name: str | None
port_slice: Iterable[PortSlice]
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
mode: Iterable[Mode]
class PowerDomains(power_domain: collections.abc.Iterable['ComponentType.PowerDomains.PowerDomain'] = <factory>)

Bases: object

Parameters:

power_domain (Iterable[PowerDomain])

class PowerDomain(name=None, display_name=None, short_description=None, description=None, always_on=None, sub_domain_of=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • always_on

  • sub_domain_of – Reference to a power domain defined on this component

  • parameters

  • vendor_extensions

  • id

Parameters:
always_on: AlwaysOn | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
sub_domain_of: str | None
vendor_extensions: VendorExtensions | None
power_domain: Iterable[PowerDomain]
class ResetTypes(reset_type=<factory>)

Bases: object

Variables:

reset_type – A user defined reset policy

Parameters:

reset_type (Iterable[ResetType])

class ResetType(name=None, display_name=None, short_description=None, description=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • vendor_extensions

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
reset_type: Iterable[ResetType]
class TypeDefinitions(external_type_definitions: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.external_type_definitions.ExternalTypeDefinitions] = <factory>)

Bases: object

Parameters:

external_type_definitions (Iterable[ExternalTypeDefinitions])

external_type_definitions: Iterable[ExternalTypeDefinitions]
address_spaces: AddressSpaces | None
assertions: Assertions | None
bus_interfaces: BusInterfaces | None
channels: Channels | None
choices: Choices | None
clearbox_elements: ClearboxElements | None
component_generators: ComponentGenerators | None
cpus: Cpus | None
description: Description | None
display_name: str | None
file_sets: FileSets | None
id: str | None
indirect_interfaces: IndirectInterfaces | None
library: str | None
memory_maps: MemoryMaps | None
model: Model | None
modes: Modes | None
name: str | None
other_clock_drivers: OtherClocks | None
parameters: Parameters | None
power_domains: PowerDomains | None
reset_types: ResetTypes | None
short_description: ShortDescription | None
type_definitions: TypeDefinitions | None
vendor: str | None
vendor_extensions: VendorExtensions | None
version: str | None

org.accellera.ipxact.v1685_2022.configurable_arrays module

class org.accellera.ipxact.v1685_2022.configurable_arrays.ConfigurableArrays(array=<factory>)

Bases: object

Variables:

array – Specific left and right array bounds.

Parameters:

array (Iterable[Array])

class Array(left: org.accellera.ipxact.v1685_2022.left.Left | None = None, right: org.accellera.ipxact.v1685_2022.right.Right | None = None, id: str | None = None)

Bases: object

Parameters:

  • left (Left | None)

  • right (Right | None)

  • id (str | None)

id: str | None
left: Left | None
right: Right | None
array: Iterable[Array]

org.accellera.ipxact.v1685_2022.configurable_element_value module

class org.accellera.ipxact.v1685_2022.configurable_element_value.ConfigurableElementValue(value='', other_attributes=<factory>, reference_id=None, id=None)

Bases: ComplexBaseExpression

Describes the content of a configurable element.

The required referenceId attribute refers to the ID attribute of the configurable element.

Variables:

  • reference_id – Refers to the ID attribute of the configurable element.

  • id

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • reference_id (str | None)

  • id (str | None)

id: str | None
other_attributes: Mapping[str, str]
reference_id: str | None
value: str

org.accellera.ipxact.v1685_2022.configurable_element_values module

class org.accellera.ipxact.v1685_2022.configurable_element_values.ConfigurableElementValues(configurable_element_value=<factory>)

Bases: object

All configuration information for a contained component, generator, generator chain or abstractor instance.

Variables:

configurable_element_value – Describes the content of a configurable element. The required referenceId attribute refers to the ID attribute of the configurable element.

Parameters:

configurable_element_value (Iterable[ConfigurableElementValue])

configurable_element_value: Iterable[ConfigurableElementValue]

org.accellera.ipxact.v1685_2022.configurable_library_ref_type module

class org.accellera.ipxact.v1685_2022.configurable_library_ref_type.ConfigurableLibraryRefType(configurable_element_values=None, vendor=None, library=None, name=None, version=None, id=None)

Bases: object

Base IP-XACT document reference type for configurable top-level objects.

Contains vendor, library, name and version attributes along with configurable element values.

Parameters:

  • configurable_element_values (ConfigurableElementValues | None)

  • vendor (str | None)

  • library (str | None)

  • name (str | None)

  • version (str | None)

  • id (str | None)

configurable_element_values: ConfigurableElementValues | None
id: str | None
library: str | None
name: str | None
vendor: str | None
version: str | None

org.accellera.ipxact.v1685_2022.constraint_set module

class org.accellera.ipxact.v1685_2022.constraint_set.ConstraintSet(name=None, display_name=None, short_description=None, description=None, vector=None, drive_constraint=None, load_constraint=None, timing_constraint=<factory>, constraint_set_id='default', id=None)

Bases: object

Defines constraints that apply to a component port.

If multiple constraintSet elements are used, each must have a unique value for the constraintSetId attribute.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • vector – The optional element vector specify the bits of a vector for which the constraints apply. The vaules of left and right must be within the range of the port. If the vector is not specified then the constraints apply to all the bits of the port.

  • drive_constraint

  • load_constraint

  • timing_constraint

  • constraint_set_id – Indicates a name for this set of constraints. Constraints are tied to a view using this name in the constraintSetRef element.

  • id

Parameters:
class Vector(left=None, right=None)

Bases: object

Variables:

  • left – The optional elements left and right can be used to select a bit-slice of a vector.

  • right – The optional elements left and right can be used to select a bit-slice of a vector.

Parameters:
left: UnsignedIntExpression | None
right: UnsignedIntExpression | None
constraint_set_id: str
description: Description | None
display_name: DisplayName | None
drive_constraint: DriveConstraint | None
id: str | None
load_constraint: LoadConstraint | None
name: str | None
short_description: ShortDescription | None
timing_constraint: Iterable[TimingConstraint]
vector: Vector | None

org.accellera.ipxact.v1685_2022.constraint_set_ref module

class org.accellera.ipxact.v1685_2022.constraint_set_ref.ConstraintSetRef(local_name=None, vendor_extensions=None, id=None)

Bases: object

A reference to a set of port constraints.

Parameters:

  • local_name (str | None)

  • vendor_extensions (VendorExtensions | None)

  • id (str | None)

id: str | None
local_name: str | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.constraint_sets module

class org.accellera.ipxact.v1685_2022.constraint_sets.ConstraintSets(constraint_set=<factory>)

Bases: object

List of constraintSet elements for a component port.

Parameters:

constraint_set (Iterable[ConstraintSet])

constraint_set: Iterable[ConstraintSet]

org.accellera.ipxact.v1685_2022.data_type_type module

class org.accellera.ipxact.v1685_2022.data_type_type.DataTypeType(*values)

Bases: Enum

Enumerates C argument data types.

CHAR = 'char *'
DOUBLE = 'double'
FLOAT = 'float'
INT = 'int'
LONG = 'long'
UNSIGNED_INT = 'unsigned int'
UNSIGNED_LONG = 'unsigned long'
VOID = 'void *'

org.accellera.ipxact.v1685_2022.default_value module

class org.accellera.ipxact.v1685_2022.default_value.DefaultValue(value='', other_attributes=<factory>)

Bases: QualifiedExpression

Default value for a wire port.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.delay_value_type module

class org.accellera.ipxact.v1685_2022.delay_value_type.DelayValueType(*values)

Bases: Enum

Indicates the type of delay value - minimum or maximum delay.

MAX = 'max'
MIN = 'min'

org.accellera.ipxact.v1685_2022.delay_value_unit_type module

class org.accellera.ipxact.v1685_2022.delay_value_unit_type.DelayValueUnitType(*values)

Bases: Enum

Indicates legal units for delay values.

NS = 'ns'
PS = 'ps'

org.accellera.ipxact.v1685_2022.dependency module

class org.accellera.ipxact.v1685_2022.dependency.Dependency(value='', id=None)

Bases: IpxactUri

Specifies a location on which files or fileSets may be dependent.

Typically, this would be a directory that would contain included files.

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str

org.accellera.ipxact.v1685_2022.description module

class org.accellera.ipxact.v1685_2022.description.Description(value='')

Bases: object

Full description string, typically for documentation.

Parameters:

value (str)

value: str

org.accellera.ipxact.v1685_2022.design module

class org.accellera.ipxact.v1685_2022.design.Design(vendor=None, library=None, name=None, version=None, display_name=None, short_description=None, description=None, component_instances=None, interconnections=None, ad_hoc_connections=None, choices=None, parameters=None, assertions=None, vendor_extensions=None, id=None)

Bases: object

Root element for a platform design.

Variables:

  • vendor – Name of the vendor who supplies this file.

  • library – Name of the logical library this element belongs to.

  • name – The name of the object.

  • version – Indicates the version of the named element.

  • display_name – Name for display purposes. Typically a few words providing a more detailed and/or user-friendly name than the vlnv.

  • short_description

  • description

  • component_instances

  • interconnections

  • ad_hoc_connections

  • choices

  • parameters

  • assertions

  • vendor_extensions

  • id

Parameters:
ad_hoc_connections: AdHocConnections | None
assertions: Assertions | None
choices: Choices | None
component_instances: ComponentInstances | None
description: Description | None
display_name: str | None
id: str | None
interconnections: Interconnections | None
library: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
vendor: str | None
vendor_extensions: VendorExtensions | None
version: str | None

org.accellera.ipxact.v1685_2022.design_configuration module

class org.accellera.ipxact.v1685_2022.design_configuration.DesignConfiguration(vendor=None, library=None, name=None, version=None, display_name=None, short_description=None, description=None, design_ref=None, generator_chain_configuration=<factory>, interconnection_configuration=<factory>, view_configuration=<factory>, choices=None, parameters=None, assertions=None, vendor_extensions=None, id=None)

Bases: object

Top level element for describing the current configuration of a design.

Does not describe instance parameterization

Variables:

  • vendor – Name of the vendor who supplies this file.

  • library – Name of the logical library this element belongs to.

  • name – The name of the object.

  • version – Indicates the version of the named element.

  • display_name – Name for display purposes. Typically a few words providing a more detailed and/or user-friendly name than the vlnv.

  • short_description

  • description

  • design_ref – The design to which this configuration applies

  • generator_chain_configuration – Contains the configurable information associated with a generatorChain and its generators. Note that configurable information for generators associated with components is stored in the design file.

  • interconnection_configuration – Contains the information about the abstractors required to cross between two interfaces at with different abstractionDefs.

  • view_configuration – Contains the active views for each instance in the design

  • choices

  • parameters

  • assertions

  • vendor_extensions

  • id

Parameters:
class InterconnectionConfiguration(interconnection_ref=None, abstractor_instances=<factory>, vendor_extensions=None, id=None)

Bases: object

Variables:

  • interconnection_ref – Reference to the interconnection name, monitor interconnection name or possibly a hierConnection interfaceName in a design file.

  • abstractor_instances – List of abstractor-instances for this interconnection. Multiple abstractor-instances elements may be present for a 1-to-many (broadcast) interconnection. In that case, the optional interfaceRef elements must reference non-overlapping interfaces from the ‘many’ side of the interconnection.

  • vendor_extensions

  • id

Parameters:
class AbstractorInstances(interface_ref=<factory>, abstractor_instance=<factory>, vendor_extensions=None, id=None)

Bases: object

Variables:

  • interface_ref – Defines the broadcast endpoint to which this chain of abstractors applies.

  • abstractor_instance – Element to hold a the abstractor reference, the configuration and viewName. If multiple elements are present then the order is the order in which the abstractors should be chained together.

  • vendor_extensions

  • id

Parameters:
class AbstractorInstance(instance_name=None, display_name=None, short_description=None, description=None, abstractor_ref=None, view_name=None, id=None)

Bases: object

Variables:

  • instance_name – Instance name for the abstractor

  • display_name

  • short_description

  • description

  • abstractor_ref – Abstractor reference

  • view_name – The name of the active view for this abstractor instance.

  • id

Parameters:
abstractor_ref: ConfigurableLibraryRefType | None
description: Description | None
display_name: DisplayName | None
id: str | None
instance_name: str | None
short_description: ShortDescription | None
view_name: str | None
class InterfaceRef(vendor_extensions=None, component_ref=None, bus_ref=None, id=None)

Bases: object

Variables:

  • vendor_extensions

  • component_ref – Reference to a component instance nane.

  • bus_ref – Reference to a component bus interface name.

  • id

Parameters:

  • vendor_extensions (VendorExtensions | None)

  • component_ref (str | None)

  • bus_ref (str | None)

  • id (str | None)

bus_ref: str | None
component_ref: str | None
id: str | None
vendor_extensions: VendorExtensions | None
abstractor_instance: Iterable[AbstractorInstance]
id: str | None
interface_ref: Iterable[InterfaceRef]
vendor_extensions: VendorExtensions | None
abstractor_instances: Iterable[AbstractorInstances]
id: str | None
interconnection_ref: str | None
vendor_extensions: VendorExtensions | None
class ViewConfiguration(instance_name=None, view=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • instance_name

  • view – The selected view for the instance.

  • vendor_extensions

  • id

Parameters:
class View(configurable_element_values=None, view_ref=None)

Bases: object

Variables:

  • configurable_element_values – Parameter values to set in the selected configuredView.

  • view_ref

Parameters:
configurable_element_values: ConfigurableElementValues | None
view_ref: str | None
id: str | None
instance_name: InstanceName | None
vendor_extensions: VendorExtensions | None
view: View | None
assertions: Assertions | None
choices: Choices | None
description: Description | None
design_ref: LibraryRefType | None
display_name: str | None
generator_chain_configuration: Iterable[ConfigurableLibraryRefType]
id: str | None
interconnection_configuration: Iterable[InterconnectionConfiguration]
library: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
vendor: str | None
vendor_extensions: VendorExtensions | None
version: str | None
view_configuration: Iterable[ViewConfiguration]

org.accellera.ipxact.v1685_2022.design_configuration_instantiation_type module

class org.accellera.ipxact.v1685_2022.design_configuration_instantiation_type.DesignConfigurationInstantiationType(name=None, display_name=None, short_description=None, description=None, language=None, design_configuration_ref=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Design configuration instantiation type.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • language – The hardware description language used such as “verilog” or “vhdl”. If the attribute “strict” is “true”, this value must match the language being generated for the design.

  • design_configuration_ref – References an IP-XACT design configuration document (by VLNV) that provides a configuration for the component’s design.

  • parameters

  • vendor_extensions

  • id

Parameters:
description: Description | None
design_configuration_ref: ConfigurableLibraryRefType | None
display_name: DisplayName | None
id: str | None
language: LanguageType | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.design_instantiation_type module

class org.accellera.ipxact.v1685_2022.design_instantiation_type.DesignInstantiationType(name=None, display_name=None, short_description=None, description=None, design_ref=None, vendor_extensions=None, id=None)

Bases: object

Design instantiation type.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • design_ref – References an IP-XACT design document (by VLNV) that provides a design for the component.

  • vendor_extensions

  • id

Parameters:
description: Description | None
design_ref: ConfigurableLibraryRefType | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.dim module

class org.accellera.ipxact.v1685_2022.dim.Dim(value='', other_attributes=<factory>, minimum=None, maximum=None, id=None, index_var=None)

Bases: UnsignedPositiveLongintExpression

Dimensions a register array, the semantics for dim elements are the same as the C language standard for the layout of memory in multidimensional arrays.

Variables:

  • id

  • index_var – Name for the index to allow referring to it in names and prosa.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

  • id (str | None)

  • index_var (str | None)

id: str | None
index_var: str | None
maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.direction module

class org.accellera.ipxact.v1685_2022.direction.Direction(*values)

Bases: Enum

IN = 'in'
INOUT = 'inout'
OUT = 'out'

org.accellera.ipxact.v1685_2022.display_name module

class org.accellera.ipxact.v1685_2022.display_name.DisplayName(value='')

Bases: object

Element name for display purposes.

Typically a few words providing a more detailed and/or user-friendly name than the ipxact:name.

Parameters:

value (str)

value: str

org.accellera.ipxact.v1685_2022.domain_type_def module

class org.accellera.ipxact.v1685_2022.domain_type_def.DomainTypeDef(type_name=None, type_definition=<factory>, view_ref=<factory>, id=None)

Bases: object

Definition of a single domain type defintion that can relate to multiple views.

Variables:

  • type_name – The name of the domain.

  • type_definition – Where the definition of the type is contained.

  • view_ref – A reference to a view in the file for which this type applies.

  • id

Parameters:
class TypeDefinition(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
class TypeName(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
class ViewRef(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
id: str | None
type_definition: Iterable[TypeDefinition]
type_name: TypeName | None
view_ref: Iterable[ViewRef]

org.accellera.ipxact.v1685_2022.domain_type_defs module

class org.accellera.ipxact.v1685_2022.domain_type_defs.DomainTypeDefs(domain_type_def=<factory>)

Bases: object

The group of domain type definitions.

Parameters:

domain_type_def (Iterable[DomainTypeDef])

domain_type_def: Iterable[DomainTypeDef]

org.accellera.ipxact.v1685_2022.drive_constraint module

class org.accellera.ipxact.v1685_2022.drive_constraint.DriveConstraint(cell_specification=None)

Bases: object

Defines a constraint indicating how an input is to be driven.

The preferred methodology is to specify a library cell in technology independent fashion. The implemention tool should assume that the associated port is driven by the specified cell, or that the drive strength of the input port is indicated by the specified resistance value.

Parameters:

cell_specification (CellSpecification | None)

cell_specification: CellSpecification | None

org.accellera.ipxact.v1685_2022.driver module

class org.accellera.ipxact.v1685_2022.driver.Driver(range=None, view_ref=<factory>, default_value=None, clock_driver=None, single_shot_driver=None, id=None)

Bases: DriverType

Wire port driver element.

Parameters:
class ViewRef(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
clock_driver: ClockDriver | None
default_value: DefaultValue | None
id: str | None
range: Range | None
single_shot_driver: SingleShotDriver | None
view_ref: Iterable['DriverType.ViewRef']

org.accellera.ipxact.v1685_2022.driver_type module

class org.accellera.ipxact.v1685_2022.driver_type.DriverType(range=None, view_ref=<factory>, default_value=None, clock_driver=None, single_shot_driver=None, id=None)

Bases: object

Wire port driver type.

Variables:

  • range

  • view_ref – A reference to a view in the file for which this type applies.

  • default_value

  • clock_driver

  • single_shot_driver

  • id

Parameters:
class ViewRef(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
clock_driver: ClockDriver | None
default_value: DefaultValue | None
id: str | None
range: Range | None
single_shot_driver: SingleShotDriver | None
view_ref: Iterable[ViewRef]

org.accellera.ipxact.v1685_2022.drivers module

class org.accellera.ipxact.v1685_2022.drivers.Drivers(driver=<factory>)

Bases: object

Container for wire port driver elements.

Variables:

driver – Wire port driver element. If no range is specified, default value applies to the entire range.

Parameters:

driver (Iterable[Driver])

driver: Iterable[Driver]

org.accellera.ipxact.v1685_2022.edge_value_type module

class org.accellera.ipxact.v1685_2022.edge_value_type.EdgeValueType(*values)

Bases: Enum

Indicates legal values for edge specification attributes.

FALL = 'fall'
RISE = 'rise'

org.accellera.ipxact.v1685_2022.endianess_type module

class org.accellera.ipxact.v1685_2022.endianess_type.EndianessType(*values)

Bases: Enum

‘big’: means the most significant element of any multi-element data field is stored at the lowest memory address.

‘little’ means the least significant element of any multi-element data field is stored at the lowest memory address. If this element is not present the default is ‘little’ endian.

BIG = 'big'
LITTLE = 'little'

org.accellera.ipxact.v1685_2022.enumerated_value_type module

class org.accellera.ipxact.v1685_2022.enumerated_value_type.EnumeratedValueType(name=None, display_name=None, short_description=None, description=None, value=None, vendor_extensions=None, usage=EnumeratedValueTypeUsage.READ_WRITE, id=None)

Bases: object

Enumerates specific values that can be assigned to the bit field.

The name of this enumerated value. This may be used as a token in generating code.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • value – Enumerated bit field value.

  • vendor_extensions

  • usage – Usage for the enumeration. ‘read’ for a software read access. ‘write’ for a software write access. ‘read-write’ for a software read or write access.

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
usage: EnumeratedValueTypeUsage
value: UnsignedBitVectorExpression | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.enumerated_value_type_usage module

class org.accellera.ipxact.v1685_2022.enumerated_value_type_usage.EnumeratedValueTypeUsage(*values)

Bases: Enum

READ = 'read'
READ_WRITE = 'read-write'
WRITE = 'write'

org.accellera.ipxact.v1685_2022.enumerated_values module

class org.accellera.ipxact.v1685_2022.enumerated_values.EnumeratedValues(enumeration_definition_ref=None, enumerated_value=<factory>)

Bases: object

Enumerates specific values that can be assigned to the bit field.

Variables:

  • enumeration_definition_ref – References an enumeration to be found in a local or external library. The four attributes define the VLNV of the referenced element.

  • enumerated_value – Enumerates specific values that can be assigned to the bit field. The name of this enumerated value. This may be used as a token in generating code.

Parameters:
class EnumerationDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
enumerated_value: Iterable[EnumeratedValueType]
enumeration_definition_ref: EnumerationDefinitionRef | None

org.accellera.ipxact.v1685_2022.enumeration_definitions module

class org.accellera.ipxact.v1685_2022.enumeration_definitions.EnumerationDefinitions(enumeration_definition: collections.abc.Iterable['EnumerationDefinitions.EnumerationDefinition'] = <factory>)

Bases: object

Parameters:

enumeration_definition (Iterable[EnumerationDefinition])

class EnumerationDefinition(name=None, display_name=None, short_description=None, description=None, width=None, enumerated_value=<factory>, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • width – Definition width used to resolve the value.

  • enumerated_value – Enumerates specific values that can be assigned to the bit field. The name of this enumerated value. This may be used as a token in generating code.

  • vendor_extensions

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
enumerated_value: Iterable[EnumeratedValueType]
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
width: UnsignedPositiveIntExpression | None
enumeration_definition: Iterable[EnumerationDefinition]

org.accellera.ipxact.v1685_2022.executable_image module

class org.accellera.ipxact.v1685_2022.executable_image.ExecutableImage(name=None, display_name=None, short_description=None, description=None, parameters=None, language_tools=None, file_set_ref_group=None, vendor_extensions=None, image_id=None, image_type=None, id=None)

Bases: object

Specifies an executable software image to be loaded into a processors address space.

The format of the image is not specified. It could, for example, be an ELF loadfile, or it could be raw binary or ascii hex data for loading directly into a memory model instance.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • parameters – Additional information about the load module, e.g. stack base addresses, table addresses, etc.

  • language_tools – Default commands and flags for software language tools needed to build the executable image.

  • file_set_ref_group – Contains a group of file set references that indicates the set of file sets complying with the tool set of the current executable image.

  • vendor_extensions

  • image_id – Unique ID for the executableImage, referenced in fileSet/function/fileRef

  • image_type – Open element to describe the type of image. The contents is model and/or generator specific.

  • id

Parameters:
class FileSetRefGroup(file_set_ref: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.file_set_ref.FileSetRef] = <factory>)

Bases: object

Parameters:

file_set_ref (Iterable[FileSetRef])

file_set_ref: Iterable[FileSetRef]
class LanguageTools(file_builder=<factory>, linker=None, linker_flags=None, linker_command_file=<factory>)

Bases: object

Variables:

  • file_builder – A generic placeholder for any file builder like compilers and assemblers. It contains the file types to which the command should be applied, and the flags to be used with that command.

  • linker

  • linker_flags

  • linker_command_file

Parameters:
class FileBuilder(file_type=None, command=None, flags=None, replace_default_flags=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • file_type

  • command – Default command used to build files of the specified fileType.

  • flags – Flags given to the build command when building files of this type.

  • replace_default_flags – If true, replace any default flags value with the value in the sibling flags element. Otherwise, append the contents of the sibling flags element to any default flags value. If the value is true and the “flags” element is empty or missing, this will have the result of clearing any default flags value.

  • vendor_extensions

  • id

Parameters:
command: StringExpression | None
file_type: FileType | None
flags: StringExpression | None
id: str | None
replace_default_flags: UnsignedBitExpression | None
vendor_extensions: VendorExtensions | None
file_builder: Iterable[FileBuilder]
linker: StringExpression | None
linker_command_file: Iterable[LinkerCommandFile]
linker_flags: StringExpression | None
description: Description | None
display_name: DisplayName | None
file_set_ref_group: FileSetRefGroup | None
id: str | None
image_id: str | None
image_type: str | None
language_tools: LanguageTools | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.extended_vectors_type module

class org.accellera.ipxact.v1685_2022.extended_vectors_type.ExtendedVectorsType(vector=<factory>)

Bases: object

Variables:

vector – Left and right ranges of the vector.

Parameters:

vector (Iterable[Vector])

class Vector(left: org.accellera.ipxact.v1685_2022.left.Left | None = None, right: org.accellera.ipxact.v1685_2022.right.Right | None = None, vector_id: str | None = None, id: str | None = None)

Bases: object

Parameters:

  • left (Left | None)

  • right (Right | None)

  • vector_id (str | None)

  • id (str | None)

id: str | None
left: Left | None
right: Right | None
vector_id: str | None
vector: Iterable[Vector]

org.accellera.ipxact.v1685_2022.external_port_reference module

class org.accellera.ipxact.v1685_2022.external_port_reference.ExternalPortReference(sub_port_reference=<factory>, part_select=None, vendor_extensions=None, port_ref=None, id=None)

Bases: object

Variables:

  • sub_port_reference

  • part_select

  • vendor_extensions

  • port_ref – A port on the on the referenced component from componentInterfaceRef.

  • id

Parameters:
id: str | None
part_select: PartSelect | None
port_ref: str | None
sub_port_reference: Iterable[SubPortReference]
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.external_type_definitions module

class org.accellera.ipxact.v1685_2022.external_type_definitions.ExternalTypeDefinitions(name=None, display_name=None, short_description=None, description=None, type_definitions_ref=None, view_links=None, mode_links=None, reset_type_links=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • type_definitions_ref – References a type definitions to be found in an external file. The four attributes define the VLNV of the referenced document.

  • view_links

  • mode_links

  • reset_type_links

  • vendor_extensions

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
type_definitions_ref: ConfigurableLibraryRefType | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.field_access_policy_definition_ref module

class org.accellera.ipxact.v1685_2022.field_access_policy_definition_ref.FieldAccessPolicyDefinitionRef(value='', type_definitions=None)

Bases: object

Indicates the accessibility of the data in the field.

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str

org.accellera.ipxact.v1685_2022.field_access_policy_definitions module

class org.accellera.ipxact.v1685_2022.field_access_policy_definitions.FieldAccessPolicyDefinitions(field_access_policy_definition: collections.abc.Iterable['FieldAccessPolicyDefinitions.FieldAccessPolicyDefinition'] = <factory>)

Bases: object

Parameters:

field_access_policy_definition (Iterable[FieldAccessPolicyDefinition])

class FieldAccessPolicyDefinition(name=None, display_name=None, short_description=None, description=None, access=None, modified_write_value=None, write_value_constraint=None, read_action=None, read_response=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access

  • modified_write_value

  • write_value_constraint

  • read_action

  • read_response

  • vendor_extensions

  • id

Parameters:
access: Access | None
description: Description | None
display_name: DisplayName | None
id: str | None
modified_write_value: ModifiedWriteValue | None
name: str | None
read_action: ReadAction | None
read_response: ReadResponse | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
write_value_constraint: WriteValueConstraint | None
field_access_policy_definition: Iterable[FieldAccessPolicyDefinition]

org.accellera.ipxact.v1685_2022.field_access_properties_type module

class org.accellera.ipxact.v1685_2022.field_access_properties_type.FieldAccessPropertiesType(id: str | None = None)

Bases: object

Parameters:

id (str | None)

id: str | None

org.accellera.ipxact.v1685_2022.field_definitions module

class org.accellera.ipxact.v1685_2022.field_definitions.FieldDefinitions(field_definition: collections.abc.Iterable['FieldDefinitions.FieldDefinition'] = <factory>)

Bases: object

Parameters:

field_definition (Iterable[FieldDefinition])

class FieldDefinition(name=None, display_name=None, short_description=None, description=None, type_identifier=None, bit_width=None, volatile=None, resets=None, field_access_policies=None, enumerated_values=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • type_identifier – Identifier name used to indicate that multiple field elements contain the exact same information for the elements in the fieldDefinitionGroup.

  • bit_width – Width of the field in bits.

  • volatile – Indicates whether the data is volatile. The presumed value is ‘false’ if not present.

  • resets

  • field_access_policies

  • enumerated_values

  • vendor_extensions

  • id

Parameters:
class FieldAccessPolicies(id: Optional[str] = None, field_access_policy: collections.abc.Iterable['FieldDefinitions.FieldDefinition.FieldAccessPolicies.FieldAccessPolicy'] = <factory>)

Bases: FieldAccessPropertiesType

Parameters:
class FieldAccessPolicy(mode_ref=<factory>, field_access_policy_definition_ref=None, access=None, modified_write_value=None, write_value_constraint=None, read_action=None, read_response=None, broadcasts=None, access_restrictions=None, testable=None, reserved=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • mode_ref

  • field_access_policy_definition_ref

  • access

  • modified_write_value

  • write_value_constraint

  • read_action

  • read_response

  • broadcasts

  • access_restrictions – Access restrictions

  • testable – Can the field be tested with an automated register test routine. The presumed value is true if not specified.

  • reserved – Indicates that the field should be documented as reserved. The presumed value is ‘0’ if not present.

  • vendor_extensions

  • id

Parameters:
class Broadcasts(broadcast_to: collections.abc.Iterable['FieldDefinitions.FieldDefinition.FieldAccessPolicies.FieldAccessPolicy.Broadcasts.BroadcastTo'] = <factory>)

Bases: object

Parameters:

broadcast_to (Iterable[BroadcastTo])

class BroadcastTo(address_space_ref: Optional[ForwardRef('FieldDefinitions.FieldDefinition.FieldAccessPolicies.FieldAccessPolicy.Broadcasts.BroadcastTo.AddressSpaceRef')] = None, memory_map_ref: Optional[ForwardRef('FieldDefinitions.FieldDefinition.FieldAccessPolicies.FieldAccessPolicy.Broadcasts.BroadcastTo.MemoryMapRef')] = None, memory_remap_ref: Optional[org.accellera.ipxact.v1685_2022.memory_remap_ref.MemoryRemapRef] = None, bank_ref: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.bank_ref.BankRef] = <factory>, address_block_ref: Optional[org.accellera.ipxact.v1685_2022.address_block_ref.AddressBlockRef] = None, register_file_ref: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.register_file_ref.RegisterFileRef] = <factory>, register_ref: Optional[org.accellera.ipxact.v1685_2022.register_ref.RegisterRef] = None, alternate_register_ref: Optional[org.accellera.ipxact.v1685_2022.alternate_register_ref.AlternateRegisterRef] = None, field_ref: Optional[org.accellera.ipxact.v1685_2022.field_ref.FieldRef] = None, id: Optional[str] = None)

Bases: object

Parameters:
class AddressSpaceRef(address_space_ref: str | None = None)

Bases: object

Parameters:

address_space_ref (str | None)

address_space_ref: str | None
class MemoryMapRef(memory_map_ref: str | None = None)

Bases: object

Parameters:

memory_map_ref (str | None)

memory_map_ref: str | None
address_block_ref: AddressBlockRef | None
address_space_ref: AddressSpaceRef | None
alternate_register_ref: AlternateRegisterRef | None
bank_ref: Iterable[BankRef]
field_ref: FieldRef | None
id: str | None
memory_map_ref: MemoryMapRef | None
memory_remap_ref: MemoryRemapRef | None
register_file_ref: Iterable[RegisterFileRef]
register_ref: RegisterRef | None
broadcast_to: Iterable[BroadcastTo]
class Testable(value=None, test_constraint=TestableTestConstraint.UNCONSTRAINED)

Bases: object

Variables:

  • value

  • test_constraint – Constraint for an automated register test routine. ‘unconstrained’ (default) means may read and write all legal values. ‘restore’ means may read and write legal values but the value must be restored to the initially read value before accessing another register. ‘writeAsRead’ has limitations on testability where only the value read before a write may be written to the field. ‘readOnly’ has limitations on testability where values may only be read from the field.

Parameters:
test_constraint: TestableTestConstraint
value: bool | None
access: Access | None
access_restrictions: AccessRestrictions | None
broadcasts: Broadcasts | None
field_access_policy_definition_ref: FieldAccessPolicyDefinitionRef | None
id: str | None
mode_ref: Iterable[ModeRef]
modified_write_value: ModifiedWriteValue | None
read_action: ReadAction | None
read_response: ReadResponse | None
reserved: UnsignedBitExpression | None
testable: Testable | None
vendor_extensions: VendorExtensions | None
write_value_constraint: WriteValueConstraint | None
field_access_policy: Iterable[FieldAccessPolicy]
id: str | None
class Resets(reset=<factory>)

Bases: object

Variables:

reset – BitField reset value

Parameters:

reset (Iterable[Reset])

reset: Iterable[Reset]
bit_width: UnsignedPositiveIntExpression | None
description: Description | None
display_name: DisplayName | None
enumerated_values: EnumeratedValues | None
field_access_policies: FieldAccessPolicies | None
id: str | None
name: str | None
resets: Resets | None
short_description: ShortDescription | None
type_identifier: str | None
vendor_extensions: VendorExtensions | None
volatile: bool | None
field_definition: Iterable[FieldDefinition]

org.accellera.ipxact.v1685_2022.field_map module

class org.accellera.ipxact.v1685_2022.field_map.FieldMap(field_slice=None, sub_port_reference=<factory>, part_select=None, mode_ref=<factory>, id=None)

Bases: object

Maps slices of this port to component field slices.

Variables:

  • field_slice – Reference to a register field slice

  • sub_port_reference

  • part_select

  • mode_ref – A reference to a mode.

  • id

Parameters:
class FieldSlice(address_space_ref: Optional[ForwardRef('FieldMap.FieldSlice.AddressSpaceRef')] = None, memory_map_ref: Optional[ForwardRef('FieldMap.FieldSlice.MemoryMapRef')] = None, memory_remap_ref: Optional[org.accellera.ipxact.v1685_2022.memory_remap_ref.MemoryRemapRef] = None, bank_ref: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.bank_ref.BankRef] = <factory>, address_block_ref: Optional[org.accellera.ipxact.v1685_2022.address_block_ref.AddressBlockRef] = None, register_file_ref: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.register_file_ref.RegisterFileRef] = <factory>, register_ref: Optional[org.accellera.ipxact.v1685_2022.register_ref.RegisterRef] = None, alternate_register_ref: Optional[org.accellera.ipxact.v1685_2022.alternate_register_ref.AlternateRegisterRef] = None, field_ref: Optional[org.accellera.ipxact.v1685_2022.field_ref.FieldRef] = None, range: Optional[org.accellera.ipxact.v1685_2022.range.Range] = None)

Bases: object

Parameters:
class AddressSpaceRef(address_space_ref: str | None = None)

Bases: object

Parameters:

address_space_ref (str | None)

address_space_ref: str | None
class MemoryMapRef(memory_map_ref: str | None = None)

Bases: object

Parameters:

memory_map_ref (str | None)

memory_map_ref: str | None
address_block_ref: AddressBlockRef | None
address_space_ref: AddressSpaceRef | None
alternate_register_ref: AlternateRegisterRef | None
bank_ref: Iterable[BankRef]
field_ref: FieldRef | None
memory_map_ref: MemoryMapRef | None
memory_remap_ref: MemoryRemapRef | None
range: Range | None
register_file_ref: Iterable[RegisterFileRef]
register_ref: RegisterRef | None
class ModeRef(value: str = '', priority: int | None = None, id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • priority (int | None)

  • id (str | None)

id: str | None
priority: int | None
value: str
field_slice: FieldSlice | None
id: str | None
mode_ref: Iterable[ModeRef]
part_select: PartSelect | None
sub_port_reference: Iterable[SubPortReference]

org.accellera.ipxact.v1685_2022.field_maps module

class org.accellera.ipxact.v1685_2022.field_maps.FieldMaps(field_map=<factory>)

Bases: object

Listing of maps between component port slices and field slices.

Parameters:

field_map (Iterable[FieldMap])

field_map: Iterable[FieldMap]

org.accellera.ipxact.v1685_2022.field_ref module

class org.accellera.ipxact.v1685_2022.field_ref.FieldRef(indices: org.accellera.ipxact.v1685_2022.indices.Indices | None = None, field_ref: str | None = None)

Bases: object

Parameters:

  • indices (Indices | None)

  • field_ref (str | None)

field_ref: str | None
indices: Indices | None

org.accellera.ipxact.v1685_2022.field_type module

class org.accellera.ipxact.v1685_2022.field_type.FieldType(name=None, display_name=None, short_description=None, description=None, access_handles=None, array=None, bit_offset=None, field_definition_ref=None, type_identifier=None, bit_width=None, volatile=None, resets=None, alias_of=None, field_access_policies=None, enumerated_values=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

A field within a register.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • array

  • bit_offset – Offset of this field’s bit 0 from bit 0 of the register.

  • field_definition_ref

  • type_identifier – Identifier name used to indicate that multiple field elements contain the exact same information for the elements in the fieldDefinitionGroup.

  • bit_width – Width of the field in bits.

  • volatile – Indicates whether the data is volatile. The presumed value is ‘false’ if not present.

  • resets

  • alias_of

  • field_access_policies

  • enumerated_values

  • parameters

  • vendor_extensions

  • id

Parameters:
class AliasOf(address_space_ref: Optional[ForwardRef('FieldType.AliasOf.AddressSpaceRef')] = None, memory_map_ref: Optional[ForwardRef('FieldType.AliasOf.MemoryMapRef')] = None, memory_remap_ref: Optional[org.accellera.ipxact.v1685_2022.memory_remap_ref.MemoryRemapRef] = None, bank_ref: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.bank_ref.BankRef] = <factory>, address_block_ref: Optional[org.accellera.ipxact.v1685_2022.address_block_ref.AddressBlockRef] = None, register_file_ref: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.register_file_ref.RegisterFileRef] = <factory>, register_ref: Optional[org.accellera.ipxact.v1685_2022.register_ref.RegisterRef] = None, alternate_register_ref: Optional[org.accellera.ipxact.v1685_2022.alternate_register_ref.AlternateRegisterRef] = None, field_ref: Optional[org.accellera.ipxact.v1685_2022.field_ref.FieldRef] = None)

Bases: object

Parameters:
class AddressSpaceRef(address_space_ref: str | None = None)

Bases: object

Parameters:

address_space_ref (str | None)

address_space_ref: str | None
class MemoryMapRef(memory_map_ref: str | None = None)

Bases: object

Parameters:

memory_map_ref (str | None)

memory_map_ref: str | None
address_block_ref: AddressBlockRef | None
address_space_ref: AddressSpaceRef | None
alternate_register_ref: AlternateRegisterRef | None
bank_ref: Iterable[BankRef]
field_ref: FieldRef | None
memory_map_ref: MemoryMapRef | None
memory_remap_ref: MemoryRemapRef | None
register_file_ref: Iterable[RegisterFileRef]
register_ref: RegisterRef | None
class Array(dim: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.dim.Dim] = <factory>, bit_stride: Optional[org.accellera.ipxact.v1685_2022.bit_stride.BitStride] = None)

Bases: object

Parameters:
bit_stride: BitStride | None
dim: Iterable[Dim]
class FieldAccessPolicies(id: Optional[str] = None, field_access_policy: collections.abc.Iterable['FieldType.FieldAccessPolicies.FieldAccessPolicy'] = <factory>)

Bases: FieldAccessPropertiesType

Parameters:
class FieldAccessPolicy(mode_ref=<factory>, field_access_policy_definition_ref=None, access=None, modified_write_value=None, write_value_constraint=None, read_action=None, read_response=None, broadcasts=None, access_restrictions=None, testable=None, reserved=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • mode_ref

  • field_access_policy_definition_ref

  • access

  • modified_write_value

  • write_value_constraint

  • read_action

  • read_response

  • broadcasts

  • access_restrictions – Access restrictions

  • testable – Can the field be tested with an automated register test routine. The presumed value is true if not specified.

  • reserved – Indicates that the field should be documented as reserved. The presumed value is ‘0’ if not present.

  • vendor_extensions

  • id

Parameters:
class Broadcasts(broadcast_to: collections.abc.Iterable['FieldType.FieldAccessPolicies.FieldAccessPolicy.Broadcasts.BroadcastTo'] = <factory>)

Bases: object

Parameters:

broadcast_to (Iterable[BroadcastTo])

class BroadcastTo(address_space_ref: Optional[ForwardRef('FieldType.FieldAccessPolicies.FieldAccessPolicy.Broadcasts.BroadcastTo.AddressSpaceRef')] = None, memory_map_ref: Optional[ForwardRef('FieldType.FieldAccessPolicies.FieldAccessPolicy.Broadcasts.BroadcastTo.MemoryMapRef')] = None, memory_remap_ref: Optional[org.accellera.ipxact.v1685_2022.memory_remap_ref.MemoryRemapRef] = None, bank_ref: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.bank_ref.BankRef] = <factory>, address_block_ref: Optional[org.accellera.ipxact.v1685_2022.address_block_ref.AddressBlockRef] = None, register_file_ref: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.register_file_ref.RegisterFileRef] = <factory>, register_ref: Optional[org.accellera.ipxact.v1685_2022.register_ref.RegisterRef] = None, alternate_register_ref: Optional[org.accellera.ipxact.v1685_2022.alternate_register_ref.AlternateRegisterRef] = None, field_ref: Optional[org.accellera.ipxact.v1685_2022.field_ref.FieldRef] = None, id: Optional[str] = None)

Bases: object

Parameters:
class AddressSpaceRef(address_space_ref: str | None = None)

Bases: object

Parameters:

address_space_ref (str | None)

address_space_ref: str | None
class MemoryMapRef(memory_map_ref: str | None = None)

Bases: object

Parameters:

memory_map_ref (str | None)

memory_map_ref: str | None
address_block_ref: AddressBlockRef | None
address_space_ref: AddressSpaceRef | None
alternate_register_ref: AlternateRegisterRef | None
bank_ref: Iterable[BankRef]
field_ref: FieldRef | None
id: str | None
memory_map_ref: MemoryMapRef | None
memory_remap_ref: MemoryRemapRef | None
register_file_ref: Iterable[RegisterFileRef]
register_ref: RegisterRef | None
broadcast_to: Iterable[BroadcastTo]
class Testable(value=None, test_constraint=TestableTestConstraint.UNCONSTRAINED)

Bases: object

Variables:

  • value

  • test_constraint – Constraint for an automated register test routine. ‘unconstrained’ (default) means may read and write all legal values. ‘restore’ means may read and write legal values but the value must be restored to the initially read value before accessing another register. ‘writeAsRead’ has limitations on testability where only the value read before a write may be written to the field. ‘readOnly’ has limitations on testability where values may only be read from the field.

Parameters:
test_constraint: TestableTestConstraint
value: bool | None
access: Access | None
access_restrictions: AccessRestrictions | None
broadcasts: Broadcasts | None
field_access_policy_definition_ref: FieldAccessPolicyDefinitionRef | None
id: str | None
mode_ref: Iterable[ModeRef]
modified_write_value: ModifiedWriteValue | None
read_action: ReadAction | None
read_response: ReadResponse | None
reserved: UnsignedBitExpression | None
testable: Testable | None
vendor_extensions: VendorExtensions | None
write_value_constraint: WriteValueConstraint | None
field_access_policy: Iterable[FieldAccessPolicy]
id: str | None
class FieldDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
class Resets(reset=<factory>)

Bases: object

Variables:

reset – BitField reset value

Parameters:

reset (Iterable[Reset])

reset: Iterable[Reset]
access_handles: AccessHandles | None
alias_of: AliasOf | None
array: Array | None
bit_offset: UnsignedIntExpression | None
bit_width: UnsignedPositiveIntExpression | None
description: Description | None
display_name: DisplayName | None
enumerated_values: EnumeratedValues | None
field_access_policies: FieldAccessPolicies | None
field_definition_ref: FieldDefinitionRef | None
id: str | None
name: str | None
parameters: Parameters | None
resets: Resets | None
short_description: ShortDescription | None
type_identifier: str | None
vendor_extensions: VendorExtensions | None
volatile: bool | None

org.accellera.ipxact.v1685_2022.file module

class org.accellera.ipxact.v1685_2022.file.File(name=None, file_type=<factory>, is_structural=None, is_include_file=None, logical_name=None, exported_name=<factory>, build_command=None, dependency=<factory>, define=<factory>, image_type=<factory>, description=None, vendor_extensions=None, file_id=None, other_attributes=<factory>, id=None)

Bases: object

IP-XACT reference to a file or directory.

Variables:

  • name – Path to the file or directory. If this path is a relative path, then it is relative to the containing XML file.

  • file_type

  • is_structural – Indicates that the current file is purely structural.

  • is_include_file – Indicate that the file is include file.

  • logical_name – Logical name for this file or directory e.g. VHDL library name.

  • exported_name – Defines exported names that can be accessed externally, e.g. exported function names from a C source file.

  • build_command – Command and flags used to build derived files from the sourceName files. If this element is present, the command and/or flags used to to build the file will override or augment any default builders at a higher level.

  • dependency

  • define – Specifies define symbols that are used in the source file. The ipxact:name element gives the name to be defined and the text content of the ipxact:value element holds the value. This element supports full configurability.

  • image_type – Relates the current file to a certain executable image type in the design.

  • description – String for describing this file to users

  • vendor_extensions

  • file_id – Unique ID for this file, referenced in fileSet/function/fileRef

  • other_attributes

  • id

Parameters:
class BuildCommand(command=None, flags=None, replace_default_flags=None, target_name=None)

Bases: object

Variables:

  • command – Command used to build this file.

  • flags – Flags given to the build command when building this file. If the optional attribute “append” is “true”, this string will be appended to any existing flags, otherwise these flags will replace any existing default flags.

  • replace_default_flags – If true, the value of the sibling element “flags” should replace any default flags specified at a more global level. If this is true and the sibling element “flags” is empty or missing, this has the effect of clearing any default flags.

  • target_name – Pathname to the file that is derived (built) from the source file.

Parameters:
class Flags(value='', other_attributes=<factory>, append=None)

Bases: StringExpression

Variables:

append – “true” indicates that the flags shall be appended to any existing flags, “false”indicates these flags will replace any existing default flags.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • append (bool | None)

append: bool | None
other_attributes: Mapping[str, str]
value: str
command: StringExpression | None
flags: Flags | None
replace_default_flags: UnsignedBitExpression | None
target_name: IpxactUri | None
class ExportedName(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
class ImageType(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
class IsIncludeFile(value=None, external_declarations=False)

Bases: object

Variables:

  • value

  • external_declarations – the File contains some declarations that are needed in top file

Parameters:

  • value (bool | None)

  • external_declarations (bool)

external_declarations: bool
value: bool | None
class LogicalName(value='', default=False)

Bases: object

Variables:

  • value

  • default – The logical name shall only be used as a default and another process may override this name.

Parameters:

  • value (str)

  • default (bool)

default: bool
value: str
build_command: BuildCommand | None
define: Iterable[NameValuePairType]
dependency: Iterable[Dependency]
description: str | None
exported_name: Iterable[ExportedName]
file_id: str | None
file_type: Iterable[FileType]
id: str | None
image_type: Iterable[ImageType]
is_include_file: IsIncludeFile | None
is_structural: bool | None
logical_name: LogicalName | None
name: IpxactUri | None
other_attributes: Mapping[str, str]
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.file_builder_type module

class org.accellera.ipxact.v1685_2022.file_builder_type.FileBuilderType(file_type=None, command=None, flags=None, replace_default_flags=None, id=None)

Bases: object

Variables:

  • file_type

  • command – Default command used to build files of the specified fileType.

  • flags – Flags given to the build command when building files of this type.

  • replace_default_flags – If true, replace any default flags value with the value in the sibling flags element. Otherwise, append the contents of the sibling flags element to any default flags value. If the value is true and the “flags” element is empty or missing, this will have the result of clearing any default flags value.

  • id

Parameters:
command: StringExpression | None
file_type: FileType | None
flags: StringExpression | None
id: str | None
replace_default_flags: UnsignedBitExpression | None

org.accellera.ipxact.v1685_2022.file_set module

class org.accellera.ipxact.v1685_2022.file_set.FileSet(name=None, display_name=None, short_description=None, description=None, group=<factory>, file=<factory>, default_file_builder=<factory>, dependency=<factory>, function=<factory>, vendor_extensions=None, id=None)

Bases: FileSetType

This element specifies a list of unique pathnames to files and directories.

It may also include build instructions for the files. If compilation order is important, e.g. for VHDL files, the files have to be provided in compilation order.

Parameters:
class Function(entry_point=None, file_ref=None, return_type=None, argument=<factory>, disabled=None, source_file=<factory>, replicate=False, id=None)

Bases: object

Variables:

  • entry_point – Optional name for the function.

  • file_ref – A reference to the file that contains the entry point function.

  • return_type – Function return type. Possible values are void and int.

  • argument – Arguments passed in when the function is called. Arguments are passed in order. This is an extension of the name-value pair which includes the data type in the ipxact:dataType attribute. The argument name is in the ipxact:name element and its value is in the ipxact:value element.

  • disabled – Specifies if the SW function is enabled. If not present the function is always enabled.

  • source_file – Location information for the source file of this function.

  • replicate – If true directs the generator to compile a separate object module for each instance of the component in the design. If false (default) the function will be called with different arguments for each instance.

  • id

Parameters:
class Argument(name=None, display_name=None, short_description=None, description=None, value=None, vendor_extensions=None, id=None, data_type=None)

Bases: NameValuePairType

Variables:

data_type – The data type of the argument as pertains to the language. Example: “int”, “double”, “char *”.

Parameters:
data_type: DataTypeType | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
value: Value | None
vendor_extensions: VendorExtensions | None
class SourceFile(source_name=None, file_type=None, id=None)

Bases: object

Variables:

  • source_name – Source file for the boot load. Relative names are searched for in the project directory and the source of the component directory.

  • file_type

  • id

Parameters:
file_type: FileType | None
id: str | None
source_name: IpxactUri | None
argument: Iterable[Argument]
disabled: UnsignedBitExpression | None
entry_point: str | None
file_ref: str | None
id: str | None
replicate: bool
return_type: ReturnTypeType | None
source_file: Iterable[SourceFile]
default_file_builder: Iterable[FileBuilderType]
dependency: Iterable[Dependency]
description: Description | None
display_name: DisplayName | None
file: Iterable[File]
function: Iterable['FileSetType.Function']
group: Iterable['FileSetType.Group']
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.file_set_ref module

class org.accellera.ipxact.v1685_2022.file_set_ref.FileSetRef(local_name=None, vendor_extensions=None, id=None)

Bases: object

A reference to a fileSet.

Variables:

  • local_name – Refers to a fileSet defined within this description.

  • vendor_extensions

  • id

Parameters:

  • local_name (str | None)

  • vendor_extensions (VendorExtensions | None)

  • id (str | None)

id: str | None
local_name: str | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.file_set_type module

class org.accellera.ipxact.v1685_2022.file_set_type.FileSetType(name=None, display_name=None, short_description=None, description=None, group=<factory>, file=<factory>, default_file_builder=<factory>, dependency=<factory>, function=<factory>, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • group – Identifies this filleSet as belonging to a particular group or having a particular purpose. Examples might be “diagnostics”, “boot”, “application”, “interrupt”, “deviceDriver”, etc.

  • file

  • default_file_builder – Default command and flags used to build derived files from the sourceName files in this file set.

  • dependency

  • function – Generator information if this file set describes a function. For example, this file set may describe diagnostics for which the DE can generate a diagnostics driver.

  • vendor_extensions

  • id

Parameters:
class Function(entry_point=None, file_ref=None, return_type=None, argument=<factory>, disabled=None, source_file=<factory>, replicate=False, id=None)

Bases: object

Variables:

  • entry_point – Optional name for the function.

  • file_ref – A reference to the file that contains the entry point function.

  • return_type – Function return type. Possible values are void and int.

  • argument – Arguments passed in when the function is called. Arguments are passed in order. This is an extension of the name-value pair which includes the data type in the ipxact:dataType attribute. The argument name is in the ipxact:name element and its value is in the ipxact:value element.

  • disabled – Specifies if the SW function is enabled. If not present the function is always enabled.

  • source_file – Location information for the source file of this function.

  • replicate – If true directs the generator to compile a separate object module for each instance of the component in the design. If false (default) the function will be called with different arguments for each instance.

  • id

Parameters:
class Argument(name=None, display_name=None, short_description=None, description=None, value=None, vendor_extensions=None, id=None, data_type=None)

Bases: NameValuePairType

Variables:

data_type – The data type of the argument as pertains to the language. Example: “int”, “double”, “char *”.

Parameters:
data_type: DataTypeType | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
value: Value | None
vendor_extensions: VendorExtensions | None
class SourceFile(source_name=None, file_type=None, id=None)

Bases: object

Variables:

  • source_name – Source file for the boot load. Relative names are searched for in the project directory and the source of the component directory.

  • file_type

  • id

Parameters:
file_type: FileType | None
id: str | None
source_name: IpxactUri | None
argument: Iterable[Argument]
disabled: UnsignedBitExpression | None
entry_point: str | None
file_ref: str | None
id: str | None
replicate: bool
return_type: ReturnTypeType | None
source_file: Iterable[SourceFile]
default_file_builder: Iterable[FileBuilderType]
dependency: Iterable[Dependency]
description: Description | None
display_name: DisplayName | None
file: Iterable[File]
function: Iterable[Function]
group: Iterable[Group]
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.file_sets module

class org.accellera.ipxact.v1685_2022.file_sets.FileSets(file_set=<factory>)

Bases: object

List of file sets associated with component.

Parameters:

file_set (Iterable[FileSet])

file_set: Iterable[FileSet]

org.accellera.ipxact.v1685_2022.file_type module

class org.accellera.ipxact.v1685_2022.file_type.FileType(value=None, user=None, libext=None, id=None)

Bases: object

Enumerated file types known by IP-XACT.

Parameters:

  • value (SimpleFileType | None)

  • user (str | None)

  • libext (str | None)

  • id (str | None)

id: str | None
libext: str | None
user: str | None
value: SimpleFileType | None

org.accellera.ipxact.v1685_2022.format_type module

class org.accellera.ipxact.v1685_2022.format_type.FormatType(*values)

Bases: Enum

This is an indication on the format of the value.

bit: 1-bit or more (vector) bits unsigned integer, byte: 8-bit signed integer, shortint: 16-bit signed integer, int: 32-bit signed integer, longint: 64-bit signed integer, shortreal: 32-bit signed floating point number, real: 64-bit signed floating point number, string: textual information.

BIT = 'bit'
BYTE = 'byte'
INT = 'int'
LONGINT = 'longint'
REAL = 'real'
SHORTINT = 'shortint'
SHORTREAL = 'shortreal'
STRING = 'string'

org.accellera.ipxact.v1685_2022.generator module

class org.accellera.ipxact.v1685_2022.generator.Generator(name=None, display_name=None, short_description=None, description=None, phase=None, parameters=None, api_type=None, api_service=None, transport_methods=None, generator_exe=None, vendor_extensions=None, hidden=False, id=None)

Bases: GeneratorType

Specifies a set of generators.

Parameters:
api_service: GeneratorTypeApiService | None
api_type: 'GeneratorType.ApiType' | None
description: Description | None
display_name: DisplayName | None
generator_exe: IpxactUri | None
hidden: bool
id: str | None
name: str | None
parameters: Parameters | None
phase: Phase | None
short_description: ShortDescription | None
transport_methods: 'GeneratorType.TransportMethods' | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.generator_chain module

class org.accellera.ipxact.v1685_2022.generator_chain.GeneratorChain(vendor=None, library=None, name=None, version=None, display_name=None, short_description=None, description=None, generator_chain_selector=<factory>, component_generator_selector=<factory>, generator=<factory>, chain_group=<factory>, choices=None, parameters=None, assertions=None, vendor_extensions=None, hidden=False, id=None)

Bases: object

Variables:

  • vendor – Name of the vendor who supplies this file.

  • library – Name of the logical library this element belongs to.

  • name – The name of the object.

  • version – Indicates the version of the named element.

  • display_name – Name for display purposes. Typically a few words providing a more detailed and/or user-friendly name than the vlnv.

  • short_description

  • description

  • generator_chain_selector – Select other generator chain files for inclusion into this chain. The boolean attribute “unique” (default false) specifies that only a single generator is valid in this context. If more that one generator is selected based on the selection criteria, DE will prompt the user to resolve to a single generator.

  • component_generator_selector – Selects generators declared in components of the current design for inclusion into this generator chain.

  • generator

  • chain_group – Identifies this generator chain as belonging to the named group. This is used by other generator chains to select this chain for programmatic inclusion.

  • choices

  • parameters

  • assertions

  • vendor_extensions

  • hidden – If this attribute is true then the generator should not be presented to the user, it may be part of a chain and has no useful meaning when invoked standalone.

  • id

Parameters:
class ChainGroup(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
class GeneratorChainSelector(group_selector=None, generator_chain_ref=None, unique=False, id=None)

Bases: object

Variables:

  • group_selector

  • generator_chain_ref – Select another generator chain using the unique identifier of this generator chain.

  • unique – Specifies that only a single generator is valid in this context. If more that one generator is selcted based on the selection criteria, DE will prompt the user to resolve to a single generator.

  • id

Parameters:
generator_chain_ref: ConfigurableLibraryRefType | None
group_selector: GroupSelector | None
id: str | None
unique: bool
assertions: Assertions | None
chain_group: Iterable[ChainGroup]
choices: Choices | None
component_generator_selector: Iterable[GeneratorSelectorType]
description: Description | None
display_name: str | None
generator: Iterable[Generator]
generator_chain_selector: Iterable[GeneratorChainSelector]
hidden: bool
id: str | None
library: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
vendor: str | None
vendor_extensions: VendorExtensions | None
version: str | None

org.accellera.ipxact.v1685_2022.generator_ref module

class org.accellera.ipxact.v1685_2022.generator_ref.GeneratorRef(value='', id=None)

Bases: object

A reference to a generator element.

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str

org.accellera.ipxact.v1685_2022.generator_selector_type module

class org.accellera.ipxact.v1685_2022.generator_selector_type.GeneratorSelectorType(group_selector: org.accellera.ipxact.v1685_2022.group_selector.GroupSelector | None = None, id: str | None = None)

Bases: object

Parameters:
group_selector: GroupSelector | None
id: str | None

org.accellera.ipxact.v1685_2022.generator_type module

class org.accellera.ipxact.v1685_2022.generator_type.GeneratorType(name=None, display_name=None, short_description=None, description=None, phase=None, parameters=None, api_type=None, api_service=None, transport_methods=None, generator_exe=None, vendor_extensions=None, hidden=False, id=None)

Bases: object

Types of generators.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • phase

  • parameters

  • api_type – Indicates the type of API used by the generator. Valid value are TGI_2009, TGI_2014_BASE, TGI_2014_EXTENDED, TGI_2022_BASE, TGI_2022_EXTENDED, and none. If this element is not present, TGI_2022_BASE is assumed. The type TGI_2009 indicates a generator using the 1685-2009 version of the TGI API. The types TGI_2014_BASE and TGI_2014_EXTENDED indicate a generator using the 1685-2014 version of the TGI API. Types TGI_2009, TGI_2014_BASE, and TGI_2014_EXTENDED are not part of the 1685-2022 version of the standard and may not be supported by Design Environments

  • api_service – Communication Mechanism. Can be one of SOAP or REST (defaults to SOAP)

  • transport_methods

  • generator_exe – The pathname to the executable file that implements the generator

  • vendor_extensions

  • hidden – If this attribute is true then the generator should not be presented to the user, it may be part of a chain and has no useful meaning when invoked standalone.

  • id

Parameters:
api_service: GeneratorTypeApiService | None
api_type: ApiType | None
description: Description | None
display_name: DisplayName | None
generator_exe: IpxactUri | None
hidden: bool
id: str | None
name: str | None
parameters: Parameters | None
phase: Phase | None
short_description: ShortDescription | None
transport_methods: TransportMethods | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.generator_type_api_service module

class org.accellera.ipxact.v1685_2022.generator_type_api_service.GeneratorTypeApiService(*values)

Bases: Enum

REST = 'REST'
SOAP = 'SOAP'

org.accellera.ipxact.v1685_2022.group module

org.accellera.ipxact.v1685_2022.group_selector module

class org.accellera.ipxact.v1685_2022.group_selector.GroupSelector(name=<factory>, multiple_group_selection_operator=GroupSelectorMultipleGroupSelectionOperator.OR, id=None)

Bases: object

Specifies a set of group names used to select subsequent generators.

The attribute “multipleGroupOperator” specifies the OR or AND selection operator if there is more than one group name (default=OR).

Variables:

  • name – Specifies a generator group name or a generator chain group name to be selected for inclusion in the generator chain.

  • multiple_group_selection_operator – Specifies the OR or AND selection operator if there is more than one group name.

  • id

Parameters:
class Name(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
id: str | None
multiple_group_selection_operator: GroupSelectorMultipleGroupSelectionOperator
name: Iterable[Name]

org.accellera.ipxact.v1685_2022.group_selector_multiple_group_selection_operator module

class org.accellera.ipxact.v1685_2022.group_selector_multiple_group_selection_operator.GroupSelectorMultipleGroupSelectionOperator(*values)

Bases: Enum

AND = 'and'
OR = 'or'

org.accellera.ipxact.v1685_2022.hier_interface_type module

class org.accellera.ipxact.v1685_2022.hier_interface_type.HierInterfaceType(description=None, vendor_extensions=None, bus_ref=None, id=None)

Bases: object

A representation of an exported interface.

The busRef indicates the name of the interface in the containing component.

Variables:

  • description

  • vendor_extensions

  • bus_ref – Reference to the components bus interface

  • id

Parameters:
bus_ref: str | None
description: Description | None
id: str | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.index module

class org.accellera.ipxact.v1685_2022.index.Index(value='', other_attributes=<factory>, minimum=None, maximum=None, id=None)

Bases: UnsignedIntExpression

An index into an object in the referenced view.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

  • id (str | None)

id: str | None
maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.indices module

class org.accellera.ipxact.v1685_2022.indices.Indices(index: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.index.Index] = <factory>)

Bases: IndicesType

Parameters:

index (Iterable[Index])

index: Iterable[Index]

org.accellera.ipxact.v1685_2022.indices_type module

class org.accellera.ipxact.v1685_2022.indices_type.IndicesType(index: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.index.Index] = <factory>)

Bases: object

Parameters:

index (Iterable[Index])

index: Iterable[Index]

org.accellera.ipxact.v1685_2022.indirect_address_ref module

class org.accellera.ipxact.v1685_2022.indirect_address_ref.IndirectAddressRef(address_space_ref=None, memory_map_ref=None, memory_remap_ref=None, bank_ref=<factory>, address_block_ref=None, register_file_ref=<factory>, register_ref=None, alternate_register_ref=None, field_ref=None)

Bases: object

A reference to a field used for addressing the indirectly accessible memoryMap.

Parameters:
class AddressSpaceRef(address_space_ref: str | None = None)

Bases: object

Parameters:

address_space_ref (str | None)

address_space_ref: str | None
class MemoryMapRef(memory_map_ref: str | None = None)

Bases: object

Parameters:

memory_map_ref (str | None)

memory_map_ref: str | None
address_block_ref: AddressBlockRef | None
address_space_ref: AddressSpaceRef | None
alternate_register_ref: AlternateRegisterRef | None
bank_ref: Iterable[BankRef]
field_ref: FieldRef | None
memory_map_ref: MemoryMapRef | None
memory_remap_ref: MemoryRemapRef | None
register_file_ref: Iterable[RegisterFileRef]
register_ref: RegisterRef | None

org.accellera.ipxact.v1685_2022.indirect_data_ref module

class org.accellera.ipxact.v1685_2022.indirect_data_ref.IndirectDataRef(address_space_ref=None, memory_map_ref=None, memory_remap_ref=None, bank_ref=<factory>, address_block_ref=None, register_file_ref=<factory>, register_ref=None, alternate_register_ref=None, field_ref=None)

Bases: object

A reference to a field used for read/write access to the indirectly accessible memoryMap.

Parameters:
class AddressSpaceRef(address_space_ref: str | None = None)

Bases: object

Parameters:

address_space_ref (str | None)

address_space_ref: str | None
class MemoryMapRef(memory_map_ref: str | None = None)

Bases: object

Parameters:

memory_map_ref (str | None)

memory_map_ref: str | None
address_block_ref: AddressBlockRef | None
address_space_ref: AddressSpaceRef | None
alternate_register_ref: AlternateRegisterRef | None
bank_ref: Iterable[BankRef]
field_ref: FieldRef | None
memory_map_ref: MemoryMapRef | None
memory_remap_ref: MemoryRemapRef | None
register_file_ref: Iterable[RegisterFileRef]
register_ref: RegisterRef | None

org.accellera.ipxact.v1685_2022.indirect_interface module

class org.accellera.ipxact.v1685_2022.indirect_interface.IndirectInterface(name=None, display_name=None, short_description=None, description=None, indirect_address_ref=None, indirect_data_ref=None, memory_map_ref=None, transparent_bridge=<factory>, bits_in_lau=None, endianness=None, parameters=None, vendor_extensions=None, id=None, any_attributes=<factory>)

Bases: IndirectInterfaceType

Describes one of the bus interfaces supported by this component.

Parameters:
any_attributes: Mapping[str, str]
bits_in_lau: BitsInLau | None
description: Description | None
display_name: DisplayName | None
endianness: EndianessType | None
id: str | None
indirect_address_ref: IndirectAddressRef | None
indirect_data_ref: IndirectDataRef | None
memory_map_ref: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
transparent_bridge: Iterable[TransparentBridge]
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.indirect_interface_type module

class org.accellera.ipxact.v1685_2022.indirect_interface_type.IndirectInterfaceType(name=None, display_name=None, short_description=None, description=None, indirect_address_ref=None, indirect_data_ref=None, memory_map_ref=None, transparent_bridge=<factory>, bits_in_lau=None, endianness=None, parameters=None, vendor_extensions=None, id=None, any_attributes=<factory>)

Bases: object

Type definition for a indirectInterface in a component.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • indirect_address_ref

  • indirect_data_ref

  • memory_map_ref – A reference to a memoryMap. This memoryMap is indirectly accessible through this interface.

  • transparent_bridge

  • bits_in_lau

  • endianness – ‘big’: means the most significant element of any multi-element data field is stored at the lowest memory address. ‘little’ means the least significant element of any multi-element data field is stored at the lowest memory address. If this element is not present the default is ‘little’ endian.

  • parameters

  • vendor_extensions

  • id

  • any_attributes

Parameters:
any_attributes: Mapping[str, str]
bits_in_lau: BitsInLau | None
description: Description | None
display_name: DisplayName | None
endianness: EndianessType | None
id: str | None
indirect_address_ref: IndirectAddressRef | None
indirect_data_ref: IndirectDataRef | None
memory_map_ref: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
transparent_bridge: Iterable[TransparentBridge]
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.indirect_interfaces module

class org.accellera.ipxact.v1685_2022.indirect_interfaces.IndirectInterfaces(indirect_interface=<factory>)

Bases: object

A list of bus interfaces supported by this component.

Parameters:

indirect_interface (Iterable[IndirectInterface])

indirect_interface: Iterable[IndirectInterface]

org.accellera.ipxact.v1685_2022.initiative module

class org.accellera.ipxact.v1685_2022.initiative.Initiative(value=None)

Bases: object

If this element is present, the type of access is restricted to the specified value.

Parameters:

value (InitiativeType | None)

value: InitiativeType | None

org.accellera.ipxact.v1685_2022.initiative_type module

class org.accellera.ipxact.v1685_2022.initiative_type.InitiativeType(*values)

Bases: Enum

BOTH = 'both'
PHANTOM = 'phantom'
PROVIDES = 'provides'
REQUIRES = 'requires'

org.accellera.ipxact.v1685_2022.instance_generator_type module

class org.accellera.ipxact.v1685_2022.instance_generator_type.InstanceGeneratorType(name=None, display_name=None, short_description=None, description=None, phase=None, parameters=None, api_type=None, api_service=None, transport_methods=None, generator_exe=None, vendor_extensions=None, hidden=False, id=None, group=<factory>, scope=InstanceGeneratorTypeScope.INSTANCE)

Bases: GeneratorType

Variables:

  • group – An identifier to specify the generator group. This is used by generator chains for selecting which generators to run.

  • scope – The scope attribute applies to component generators and specifies whether the generator should be run for each instance of the entity (or module) or just once for all instances of the entity.

Parameters:
api_service: GeneratorTypeApiService | None
api_type: 'GeneratorType.ApiType' | None
description: Description | None
display_name: DisplayName | None
generator_exe: IpxactUri | None
group: Iterable[InstanceGeneratorType.Group]
hidden: bool
id: str | None
name: str | None
parameters: Parameters | None
phase: Phase | None
scope: InstanceGeneratorTypeScope
short_description: ShortDescription | None
transport_methods: 'GeneratorType.TransportMethods' | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.instance_generator_type_scope module

class org.accellera.ipxact.v1685_2022.instance_generator_type_scope.InstanceGeneratorTypeScope(*values)

Bases: Enum

ENTITY = 'entity'
INSTANCE = 'instance'

org.accellera.ipxact.v1685_2022.instance_name module

class org.accellera.ipxact.v1685_2022.instance_name.InstanceName(value='')

Bases: object

An instance name assigned to subcomponent instances and contained channels, that is unique within the parent component.

Parameters:

value (str)

value: str

org.accellera.ipxact.v1685_2022.interconnection module

class org.accellera.ipxact.v1685_2022.interconnection.Interconnection(name=None, display_name=None, short_description=None, description=None, active_interface=<factory>, hier_interface=<factory>, vendor_extensions=None, id=None)

Bases: object

Describes a connection between two active (not monitor) busInterfaces.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • active_interface – Describes one interface of the interconnection. The componentInterfaceRef and busRef attributes indicate the instance name and bus interface name of one end of the connection. This interface can be connected to one or more additional active and/or hierarchical interfaces, or to one or more hierarchical interfaces or to one or more monitor interfaces. The connected interfaces are all contained within the choice element below.

  • hier_interface

  • vendor_extensions

  • id

Parameters:
active_interface: Iterable[ActiveInterface]
description: Description | None
display_name: DisplayName | None
hier_interface: Iterable[HierInterfaceType]
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.interconnections module

class org.accellera.ipxact.v1685_2022.interconnections.Interconnections(interconnection=<factory>, monitor_interconnection=<factory>)

Bases: object

Connections between internal sub components.

Parameters:
interconnection: Iterable[Interconnection]
monitor_interconnection: Iterable[MonitorInterconnection]

org.accellera.ipxact.v1685_2022.interface_type module

class org.accellera.ipxact.v1685_2022.interface_type.InterfaceType(component_instance_ref=None, bus_ref=None, id=None)

Bases: object

A representation of a component/bus interface relation; i.e. a bus interface belonging to a certain component.

Variables:

  • component_instance_ref – Reference to a component instance name.

  • bus_ref – Reference to the components bus interface

  • id

Parameters:

  • component_instance_ref (str | None)

  • bus_ref (str | None)

  • id (str | None)

bus_ref: str | None
component_instance_ref: str | None
id: str | None

org.accellera.ipxact.v1685_2022.ipxact_file_type module

class org.accellera.ipxact.v1685_2022.ipxact_file_type.IpxactFileType(vlnv=None, name=None, description=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • vlnv – VLNV of the IP-XACT file being cataloged.

  • name – Name of the IP-XACT file being cataloged.

  • description

  • vendor_extensions

  • id

Parameters:
description: Description | None
id: str | None
name: IpxactUri | None
vendor_extensions: VendorExtensions | None
vlnv: LibraryRefType | None

org.accellera.ipxact.v1685_2022.ipxact_files_type module

class org.accellera.ipxact.v1685_2022.ipxact_files_type.IpxactFilesType(ipxact_file=<factory>)

Bases: object

Contains a list of IP-XACT files to include.

Parameters:

ipxact_file (Iterable[IpxactFileType])

ipxact_file: Iterable[IpxactFileType]

org.accellera.ipxact.v1685_2022.ipxact_uri module

class org.accellera.ipxact.v1685_2022.ipxact_uri.IpxactUri(value='')

Bases: object

IP-XACT URI, like a standard xs:anyURI except that it can contain environment variables in the ${ } form, to be replaced by their value to provide the underlying URI.

Parameters:

value (str)

value: str

org.accellera.ipxact.v1685_2022.is_clock_en_level module

class org.accellera.ipxact.v1685_2022.is_clock_en_level.IsClockEnLevel(*values)

Bases: Enum

HIGH = 'high'
LOW = 'low'

org.accellera.ipxact.v1685_2022.is_flow_control_flow_type module

class org.accellera.ipxact.v1685_2022.is_flow_control_flow_type.IsFlowControlFlowType(*values)

Bases: Enum

BUSY = 'busy'
CREDIT_RETURN = 'credit-return'
READY = 'ready'
USER = 'user'

org.accellera.ipxact.v1685_2022.is_power_en_level module

class org.accellera.ipxact.v1685_2022.is_power_en_level.IsPowerEnLevel(*values)

Bases: Enum

HIGH = 'high'
LOW = 'low'

org.accellera.ipxact.v1685_2022.is_reset_level module

class org.accellera.ipxact.v1685_2022.is_reset_level.IsResetLevel(*values)

Bases: Enum

HIGH = 'high'
LOW = 'low'

org.accellera.ipxact.v1685_2022.kind module

class org.accellera.ipxact.v1685_2022.kind.Kind(value=None, custom=None)

Bases: object

Defines the protocol type.

Defaults to tlm_base_protocol_type for TLM sockets

Parameters:

  • value (KindType | None)

  • custom (str | None)

custom: str | None
value: KindType | None

org.accellera.ipxact.v1685_2022.kind_type module

class org.accellera.ipxact.v1685_2022.kind_type.KindType(*values)

Bases: Enum

CUSTOM = 'custom'
MULTI_SOCKET = 'multi_socket'
SIMPLE_SOCKET = 'simple_socket'
TLM_PORT = 'tlm_port'
TLM_SOCKET = 'tlm_socket'

org.accellera.ipxact.v1685_2022.language_type module

class org.accellera.ipxact.v1685_2022.language_type.LanguageType(value='', strict=False)

Bases: object

Variables:

  • value

  • strict – A value of ‘true’ indicates that this value must match the language being generated for the design.

Parameters:

  • value (str)

  • strict (bool)

strict: bool
value: str

org.accellera.ipxact.v1685_2022.left module

class org.accellera.ipxact.v1685_2022.left.Left(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: UnsignedIntExpression

The optional element left specifies the left boundary.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.library_ref_type module

class org.accellera.ipxact.v1685_2022.library_ref_type.LibraryRefType(vendor=None, library=None, name=None, version=None, id=None)

Bases: object

Base IP-XACT document reference type.

Contains vendor, library, name and version attributes.

Parameters:

  • vendor (str | None)

  • library (str | None)

  • name (str | None)

  • version (str | None)

  • id (str | None)

id: str | None
library: str | None
name: str | None
vendor: str | None
version: str | None

org.accellera.ipxact.v1685_2022.linker_command_file module

class org.accellera.ipxact.v1685_2022.linker_command_file.LinkerCommandFile(name=None, command_line_switch=None, enable=None, generator_ref=<factory>, vendor_extensions=None, id=None)

Bases: object

Specifies a linker command file.

Variables:

  • name – Linker command file name.

  • command_line_switch – The command line switch to specify the linker command file.

  • enable – Specifies whether to generate and enable the linker command file.

  • generator_ref

  • vendor_extensions

  • id

Parameters:
command_line_switch: StringExpression | None
enable: UnsignedBitExpression | None
generator_ref: Iterable[GeneratorRef]
id: str | None
name: StringExpression | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.load_constraint module

class org.accellera.ipxact.v1685_2022.load_constraint.LoadConstraint(cell_specification=None, count=None)

Bases: object

Defines a constraint indicating the type of load on an output port.

Variables:

  • cell_specification

  • count – Indicates how many loads of the specified cell are connected. If not present, 3 is assumed.

Parameters:
cell_specification: CellSpecification | None
count: UnsignedPositiveIntExpression | None

org.accellera.ipxact.v1685_2022.local_address_bank_type module

class org.accellera.ipxact.v1685_2022.local_address_bank_type.LocalAddressBankType(name=None, display_name=None, short_description=None, description=None, access_handles=None, base_address=None, address_block=<factory>, bank=<factory>, usage=None, volatile=None, access_policies=None, parameters=None, vendor_extensions=None, bank_alignment=None, id=None)

Bases: object

Top level bank the specify an address.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • base_address

  • address_block – An address block within the bank. No address information is supplied.

  • bank – A nested bank of blocks within a bank. No address information is supplied.

  • usage – Indicates the usage of this block. Possible values are ‘memory’, ‘register’ and ‘reserved’.

  • volatile

  • access_policies

  • parameters – Any additional parameters needed to describe this address block to the generators.

  • vendor_extensions

  • bank_alignment – Describes whether this bank’s blocks are aligned in ‘parallel’ or ‘serial’.

  • id

Parameters:
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_block: Iterable[BankedBlockType]
bank: Iterable[LocalBankedBankType]
bank_alignment: BankAlignmentType | None
base_address: BaseAddress | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
usage: UsageType | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None

org.accellera.ipxact.v1685_2022.local_banked_bank_type module

class org.accellera.ipxact.v1685_2022.local_banked_bank_type.LocalBankedBankType(name=None, display_name=None, short_description=None, description=None, access_handles=None, address_block=<factory>, bank=<factory>, usage=None, volatile=None, access_policies=None, parameters=None, vendor_extensions=None, bank_alignment=None, id=None)

Bases: object

Banks nested inside a bank do not specify address.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • address_block – An address block within the bank. No address information is supplied.

  • bank – A nested bank of blocks within a bank. No address information is supplied.

  • usage – Indicates the usage of this block. Possible values are ‘memory’, ‘register’ and ‘reserved’.

  • volatile

  • access_policies

  • parameters – Any additional parameters needed to describe this address block to the generators.

  • vendor_extensions

  • bank_alignment

  • id

Parameters:
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_block: Iterable[BankedBlockType]
bank: Iterable[LocalBankedBankType]
bank_alignment: BankAlignmentType | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
usage: UsageType | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None

org.accellera.ipxact.v1685_2022.local_memory_map_type module

class org.accellera.ipxact.v1685_2022.local_memory_map_type.LocalMemoryMapType(name=None, display_name=None, short_description=None, description=None, address_block=<factory>, bank=<factory>, vendor_extensions=None, id=None)

Bases: object

Map of address space blocks on the local memory map of a initiator bus interface.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • address_block

  • bank – Represents a bank of memory made up of address blocks or other banks. It has a bankAlignment attribute indicating whether its blocks are aligned in ‘parallel’ (occupying adjacent bit fields) or ‘serial’ (occupying contiguous addresses). Its child blocks do not contain addresses or bit offsets.

  • vendor_extensions

  • id

Parameters:
address_block: Iterable[AddressBlock]
bank: Iterable[LocalAddressBankType]
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.memory_map_definitions module

class org.accellera.ipxact.v1685_2022.memory_map_definitions.MemoryMapDefinitions(memory_map_definition: collections.abc.Iterable['MemoryMapDefinitions.MemoryMapDefinition'] = <factory>)

Bases: object

Parameters:

memory_map_definition (Iterable[MemoryMapDefinition])

class MemoryMapDefinition(name=None, display_name=None, short_description=None, description=None, address_block=<factory>, bank=<factory>, memory_remap=<factory>, address_unit_bits=None, shared=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • address_block

  • bank – An addressable bank of blocks within a bank definition.

  • memory_remap

  • address_unit_bits

  • shared – When the value is ‘yes’, the contents of the memoryMap are shared by all the references to this memoryMap, when the value is ‘no’ the contents of the memoryMap is not shared and when the value is ‘undefined’ (default) the sharing of the memoryMap is undefined.

  • vendor_extensions

  • id

Parameters:
address_block: Iterable[AddressBlock]
address_unit_bits: AddressUnitBits | None
bank: Iterable[AddressBankDefinitionType]
description: Description | None
display_name: DisplayName | None
id: str | None
memory_remap: Iterable[MemoryRemapDefinitionType]
name: str | None
shared: SharedType | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
memory_map_definition: Iterable[MemoryMapDefinition]

org.accellera.ipxact.v1685_2022.memory_map_ref module

class org.accellera.ipxact.v1685_2022.memory_map_ref.MemoryMapRef(mode_ref=<factory>, memory_map_ref=None)

Bases: MemoryMapRefType

References the memory map.

The name of the memory map is kept in its memoryMapRef attribute.

Parameters:

  • mode_ref (Iterable[ModeRef])

  • memory_map_ref (str | None)

class ModeRef(value='', id=None)

Bases: object

A reference to a mode.

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
memory_map_ref: str | None
mode_ref: Iterable['MemoryMapRefType.ModeRef']

org.accellera.ipxact.v1685_2022.memory_map_ref_type module

class org.accellera.ipxact.v1685_2022.memory_map_ref_type.MemoryMapRefType(mode_ref=<factory>, memory_map_ref=None)

Bases: object

Base type for an element which references an memory map.

Reference is kept in an attribute rather than the text value, so that the type may be extended with child elements if necessary.

Variables:

  • mode_ref

  • memory_map_ref – A reference to a unique memory map.

Parameters:

  • mode_ref (Iterable[ModeRef])

  • memory_map_ref (str | None)

class ModeRef(value='', id=None)

Bases: object

A reference to a mode.

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
memory_map_ref: str | None
mode_ref: Iterable[ModeRef]

org.accellera.ipxact.v1685_2022.memory_map_type module

class org.accellera.ipxact.v1685_2022.memory_map_type.MemoryMapType(name=None, display_name=None, short_description=None, description=None, memory_map_definition_ref=None, address_block=<factory>, bank=<factory>, subspace_map=<factory>, memory_remap=<factory>, address_unit_bits=None, shared=None, vendor_extensions=None, id=None)

Bases: object

Map of address space blocks on target target bus interface.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • memory_map_definition_ref

  • address_block

  • bank

  • subspace_map

  • memory_remap

  • address_unit_bits

  • shared – When the value is ‘yes’, the contents of the memoryMap are shared by all the references to this memoryMap, when the value is ‘no’ the contents of the memoryMap is not shared and when the value is ‘undefined’ (default) the sharing of the memoryMap is undefined.

  • vendor_extensions

  • id

Parameters:
class MemoryMapDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
address_block: Iterable[AddressBlock]
address_unit_bits: AddressUnitBits | None
bank: Iterable[Bank]
description: Description | None
display_name: DisplayName | None
id: str | None
memory_map_definition_ref: MemoryMapDefinitionRef | None
memory_remap: Iterable[MemoryRemap]
name: str | None
shared: SharedType | None
short_description: ShortDescription | None
subspace_map: Iterable[SubspaceMap]
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.memory_maps module

class org.accellera.ipxact.v1685_2022.memory_maps.MemoryMaps(memory_map=<factory>)

Bases: object

Lists all the target memory maps defined by the component.

Variables:

memory_map – The set of address blocks a bus target contributes to the bus’ address space.

Parameters:

memory_map (Iterable[MemoryMapType])

memory_map: Iterable[MemoryMapType]

org.accellera.ipxact.v1685_2022.memory_remap module

class org.accellera.ipxact.v1685_2022.memory_remap.MemoryRemap(name=None, display_name=None, short_description=None, description=None, mode_ref=<factory>, remap_definition_ref=None, address_block=<factory>, bank=<factory>, subspace_map=<factory>, vendor_extensions=None, id=None)

Bases: MemoryRemapType

Additional memory map elements that are dependent on the component state.

Parameters:
class RemapDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
address_block: Iterable[AddressBlock]
bank: Iterable[Bank]
description: Description | None
display_name: DisplayName | None
id: str | None
mode_ref: Iterable[ModeRef]
name: str | None
remap_definition_ref: 'MemoryRemapType.RemapDefinitionRef' | None
short_description: ShortDescription | None
subspace_map: Iterable[SubspaceMap]
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.memory_remap_definition_type module

class org.accellera.ipxact.v1685_2022.memory_remap_definition_type.MemoryRemapDefinitionType(name=None, display_name=None, short_description=None, description=None, mode_ref=<factory>, remap_definition_ref=None, address_block=<factory>, bank=<factory>, vendor_extensions=None, id=None)

Bases: object

Map of address space blocks on a target bus interface in a specific remap state.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • mode_ref

  • remap_definition_ref

  • address_block – An address block within the bank. No address information is supplied.

  • bank – A nested bank of blocks within a bank. No address information is supplied.

  • vendor_extensions

  • id

Parameters:
class RemapDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
address_block: Iterable[AddressBlockType]
bank: Iterable[Bank]
description: Description | None
display_name: DisplayName | None
id: str | None
mode_ref: Iterable[ModeRef]
name: str | None
remap_definition_ref: RemapDefinitionRef | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.memory_remap_definitions module

class org.accellera.ipxact.v1685_2022.memory_remap_definitions.MemoryRemapDefinitions(memory_remap_definition: collections.abc.Iterable['MemoryRemapDefinitions.MemoryRemapDefinition'] = <factory>)

Bases: object

Parameters:

memory_remap_definition (Iterable[MemoryRemapDefinition])

class MemoryRemapDefinition(name=None, display_name=None, short_description=None, description=None, address_block=<factory>, bank=<factory>, address_unit_bits=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • address_block

  • bank – An addressable bank of blocks within a bank definition.

  • address_unit_bits

  • vendor_extensions

  • id

Parameters:
address_block: Iterable[AddressBlock]
address_unit_bits: AddressUnitBits | None
bank: Iterable[AddressBankDefinitionType]
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
memory_remap_definition: Iterable[MemoryRemapDefinition]

org.accellera.ipxact.v1685_2022.memory_remap_ref module

class org.accellera.ipxact.v1685_2022.memory_remap_ref.MemoryRemapRef(memory_remap_ref: str | None = None)

Bases: object

Parameters:

memory_remap_ref (str | None)

memory_remap_ref: str | None

org.accellera.ipxact.v1685_2022.memory_remap_type module

class org.accellera.ipxact.v1685_2022.memory_remap_type.MemoryRemapType(name=None, display_name=None, short_description=None, description=None, mode_ref=<factory>, remap_definition_ref=None, address_block=<factory>, bank=<factory>, subspace_map=<factory>, vendor_extensions=None, id=None)

Bases: object

Map of address space blocks on a target bus interface in a specific remap state.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • mode_ref

  • remap_definition_ref

  • address_block

  • bank

  • subspace_map

  • vendor_extensions

  • id

Parameters:
class RemapDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
address_block: Iterable[AddressBlock]
bank: Iterable[Bank]
description: Description | None
display_name: DisplayName | None
id: str | None
mode_ref: Iterable[ModeRef]
name: str | None
remap_definition_ref: RemapDefinitionRef | None
short_description: ShortDescription | None
subspace_map: Iterable[SubspaceMap]
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.mode_ref module

class org.accellera.ipxact.v1685_2022.mode_ref.ModeRef(value='', priority=None, id=None)

Bases: object

A reference to a mode.

Parameters:

  • value (str)

  • priority (int | None)

  • id (str | None)

id: str | None
priority: int | None
value: str

org.accellera.ipxact.v1685_2022.model module

class org.accellera.ipxact.v1685_2022.model.Model(views=None, instantiations=None, ports=None)

Bases: ModelType

Model information.

Parameters:
class Instantiations(component_instantiation=<factory>, design_instantiation=<factory>, design_configuration_instantiation=<factory>)

Bases: object

Variables:

  • component_instantiation – Component Instantiation

  • design_instantiation – Design Instantiation

  • design_configuration_instantiation – Design Configuration Instantiation

Parameters:
component_instantiation: Iterable[ComponentInstantiationType]
design_configuration_instantiation: Iterable[DesignConfigurationInstantiationType]
design_instantiation: Iterable[DesignInstantiationType]
class Ports(port: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.port.Port] = <factory>)

Bases: object

Parameters:

port (Iterable[Port])

port: Iterable[Port]
class Views(view=<factory>)

Bases: object

Variables:

view – Single view of a component

Parameters:

view (Iterable[View])

class View(name=None, display_name=None, short_description=None, description=None, env_identifier=<factory>, component_instantiation_ref=None, design_instantiation_ref=None, design_configuration_instantiation_ref=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • env_identifier – Defines the hardware environment in which this view applies. The format of the string is language:tool:vendor_extension, with each piece being optional. The language must be one of the types from ipxact:fileType. The tool values are defined by the Accellera Systems Initiative, and include generic values “*Simulation” and “*Synthesis” to imply any tool of the indicated type. Having more than one envIdentifier indicates that the view applies to multiple environments.

  • component_instantiation_ref

  • design_instantiation_ref

  • design_configuration_instantiation_ref

  • vendor_extensions

  • id

Parameters:

  • name (str | None)

  • display_name (DisplayName | None)

  • short_description (ShortDescription | None)

  • description (Description | None)

  • env_identifier (Iterable[EnvIdentifier])

  • component_instantiation_ref (str | None)

  • design_instantiation_ref (str | None)

  • design_configuration_instantiation_ref (str | None)

  • vendor_extensions (VendorExtensions | None)

  • id (str | None)

class EnvIdentifier(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
component_instantiation_ref: str | None
description: Description | None
design_configuration_instantiation_ref: str | None
design_instantiation_ref: str | None
display_name: DisplayName | None
env_identifier: Iterable[EnvIdentifier]
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
view: Iterable[View]
instantiations: 'ModelType.Instantiations' | None
ports: 'ModelType.Ports' | None
views: 'ModelType.Views' | None

org.accellera.ipxact.v1685_2022.model_type module

class org.accellera.ipxact.v1685_2022.model_type.ModelType(views=None, instantiations=None, ports=None)

Bases: object

Model information.

Variables:

  • views – Views container

  • instantiations – Instantiations container

  • ports – Port container

Parameters:
class Instantiations(component_instantiation=<factory>, design_instantiation=<factory>, design_configuration_instantiation=<factory>)

Bases: object

Variables:

  • component_instantiation – Component Instantiation

  • design_instantiation – Design Instantiation

  • design_configuration_instantiation – Design Configuration Instantiation

Parameters:
component_instantiation: Iterable[ComponentInstantiationType]
design_configuration_instantiation: Iterable[DesignConfigurationInstantiationType]
design_instantiation: Iterable[DesignInstantiationType]
class Ports(port: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.port.Port] = <factory>)

Bases: object

Parameters:

port (Iterable[Port])

port: Iterable[Port]
class Views(view=<factory>)

Bases: object

Variables:

view – Single view of a component

Parameters:

view (Iterable[View])

class View(name=None, display_name=None, short_description=None, description=None, env_identifier=<factory>, component_instantiation_ref=None, design_instantiation_ref=None, design_configuration_instantiation_ref=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • env_identifier – Defines the hardware environment in which this view applies. The format of the string is language:tool:vendor_extension, with each piece being optional. The language must be one of the types from ipxact:fileType. The tool values are defined by the Accellera Systems Initiative, and include generic values “*Simulation” and “*Synthesis” to imply any tool of the indicated type. Having more than one envIdentifier indicates that the view applies to multiple environments.

  • component_instantiation_ref

  • design_instantiation_ref

  • design_configuration_instantiation_ref

  • vendor_extensions

  • id

Parameters:

  • name (str | None)

  • display_name (DisplayName | None)

  • short_description (ShortDescription | None)

  • description (Description | None)

  • env_identifier (Iterable[EnvIdentifier])

  • component_instantiation_ref (str | None)

  • design_instantiation_ref (str | None)

  • design_configuration_instantiation_ref (str | None)

  • vendor_extensions (VendorExtensions | None)

  • id (str | None)

class EnvIdentifier(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
component_instantiation_ref: str | None
description: Description | None
design_configuration_instantiation_ref: str | None
design_instantiation_ref: str | None
display_name: DisplayName | None
env_identifier: Iterable[EnvIdentifier]
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
view: Iterable[View]
instantiations: Instantiations | None
ports: Ports | None
views: Views | None

org.accellera.ipxact.v1685_2022.modified_write_value module

class org.accellera.ipxact.v1685_2022.modified_write_value.ModifiedWriteValue(value=None, modify=None)

Bases: object

If present this element describes the modification of field data caused by a write operation.

‘oneToClear’ means that in a bitwise fashion each write data bit of a one will clear the corresponding bit in the field. ‘oneToSet’ means that in a bitwise fashion each write data bit of a one will set the corresponding bit in the field. ‘oneToToggle’ means that in a bitwise fashion each write data bit of a one will toggle the corresponding bit in the field. ‘zeroToClear’ means that in a bitwise fashion each write data bit of a zero will clear the corresponding bit in the field. ‘zeroToSet’ means that in a bitwise fashion each write data bit of a zero will set the corresponding bit in the field. ‘zeroToToggle’ means that in a bitwise fashion each write data bit of a zero will toggle the corresponding bit in the field. ‘clear’ means any write to this field clears the field. ‘set’ means any write to the field sets the field. ‘modify’ means any write to this field may modify that data. If this element is not present the write operation data is written.

Parameters:
modify: str | None
value: ModifiedWriteValueType | None

org.accellera.ipxact.v1685_2022.modified_write_value_type module

class org.accellera.ipxact.v1685_2022.modified_write_value_type.ModifiedWriteValueType(*values)

Bases: Enum

CLEAR = 'clear'
MODIFY = 'modify'
ONE_TO_CLEAR = 'oneToClear'
ONE_TO_SET = 'oneToSet'
ONE_TO_TOGGLE = 'oneToToggle'
SET = 'set'
ZERO_TO_CLEAR = 'zeroToClear'
ZERO_TO_SET = 'zeroToSet'
ZERO_TO_TOGGLE = 'zeroToToggle'

org.accellera.ipxact.v1685_2022.module_parameter_arrays module

class org.accellera.ipxact.v1685_2022.module_parameter_arrays.ModuleParameterArrays(array=<factory>)

Bases: object

Variables:

array – Specific left and right array bounds.

Parameters:

array (Iterable[Array])

class Array(left: org.accellera.ipxact.v1685_2022.left.Left | None = None, right: org.accellera.ipxact.v1685_2022.right.Right | None = None, array_id: str | None = None, id: str | None = None)

Bases: object

Parameters:

  • left (Left | None)

  • right (Right | None)

  • array_id (str | None)

  • id (str | None)

array_id: str | None
id: str | None
left: Left | None
right: Right | None
array: Iterable[Array]

org.accellera.ipxact.v1685_2022.module_parameter_type module

class org.accellera.ipxact.v1685_2022.module_parameter_type.ModuleParameterType(name=None, display_name=None, short_description=None, description=None, vectors=None, arrays=None, value=None, vendor_extensions=None, id=None, parameter_id=None, prompt=None, choice_ref=None, order=None, config_groups=<factory>, minimum=None, maximum=None, type_value=FormatType.STRING, sign=None, prefix=None, unit=None, resolve=ModuleParameterTypeResolve.IMMEDIATE, other_attributes=<factory>, data_type=None, usage_type=ModuleParameterTypeUsageType.TYPED, data_type_definition=None, constrained=<factory>)

Bases: object

Name value pair with data type information.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • vectors

  • arrays

  • value

  • vendor_extensions

  • id

  • parameter_id – ID attribute for uniquely identifying a parameter within its document. Attribute is used to refer to this from a configurable element.

  • prompt – Provides a string used to prompt the user for user- resolved property values.

  • choice_ref – For user defined properties, refers the choice element enumerating the values to choose from.

  • order – For components with auto-generated configuration forms, the user-resolved properties with order attibutes will be presented in ascending order.

  • config_groups – Tags configurable properties so that they may be grouped together. Configurable properties with matching values for this attribute are contained in the same group. The format of this attribute is a string. There is no semantic meaning to this attribute.

  • minimum – For user-resolved properties with numeric values, this indicates the minimum value allowed. Only valid for the types: byte, shortint, int, longint, shortreal and real. The type of this value is the same as the type of the parameter- value, which is specified by the parameter-type attribute.

  • maximum – For user-resolved properties with numeric values, this indicates the maximum value allowed. Only valid for the types: byte, shortint, int, longint, shortreal and real. The type of this value is the same as the type of the parameter- value, which is specified by the parameter-type attribute.

  • type_value – Specifies the type of the value of the parameter. A parameter of type byte is resolved to an 8-bit integer value, shortint is resolved to a 16-bit integer value, int is resolved to a 32-bit integer value, longint is resolved to a 64-bit integer value, shortreal is resolved to a 32-bit floating point value, real is resolved to a 64-bit floating point value, bit is by default resolved to a one bit value, unless a vector size has been specified and the string type is resolved to a string value.

  • sign – Specify the signedness explicitly. The data types byte, shortint, int, longint default to signed. The data type bit defaults to unsigned. When setting this values for the data types string, real and shortreal the setting is ignored.

  • prefix – Defines the prefix that precedes the unit of a value. The prefix is not applied to the value (e.g. in calculations).

  • unit – Defines the unit of the value.

  • resolve – Determines how a property value can be configured.

  • other_attributes

  • data_type – The data type of the argument as pertains to the language. Example: “int”, “double”, “char *”.

  • usage_type – Indicates the type of the module parameter. Legal values are defined in the attribute enumeration list. Default value is ‘typed’.

  • data_type_definition – The dataTypeDefinition references a file, which is included in the filesetRef referenced from the componentInstantiation.

  • constrained – Indicates for which vectors and arrays the number of bits in the type declaration is fixed by referencing the vectorId and arrayId values. The values are separated by whitespace.

Parameters:
class Vectors(vector=<factory>)

Bases: object

Variables:

vector – Left and right ranges of the vector.

Parameters:

vector (Iterable[Vector])

class Vector(left: org.accellera.ipxact.v1685_2022.left.Left | None = None, right: org.accellera.ipxact.v1685_2022.right.Right | None = None, vector_id: str | None = None, id: str | None = None)

Bases: object

Parameters:

  • left (Left | None)

  • right (Right | None)

  • vector_id (str | None)

  • id (str | None)

id: str | None
left: Left | None
right: Right | None
vector_id: str | None
vector: Iterable[Vector]
arrays: ModuleParameterArrays | None
choice_ref: str | None
config_groups: Iterable[str]
constrained: Iterable[str]
data_type: str | None
data_type_definition: str | None
description: Description | None
display_name: DisplayName | None
id: str | None
maximum: str | None
minimum: str | None
name: str | None
order: float | None
other_attributes: Mapping[str, str]
parameter_id: str | None
prefix: ModuleParameterTypePrefix | None
prompt: str | None
resolve: ModuleParameterTypeResolve
short_description: ShortDescription | None
sign: SignType | None
type_value: FormatType
unit: ModuleParameterTypeUnit | None
usage_type: ModuleParameterTypeUsageType
value: Value | None
vectors: Vectors | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.module_parameter_type_prefix module

class org.accellera.ipxact.v1685_2022.module_parameter_type_prefix.ModuleParameterTypePrefix(*values)

Bases: Enum

ATTO = 'atto'
CENTI = 'centi'
DECA = 'deca'
DECI = 'deci'
EXA = 'exa'
FEMTO = 'femto'
GIGA = 'giga'
HECTO = 'hecto'
KILO = 'kilo'
MEGA = 'mega'
MICRO = 'micro'
MILLI = 'milli'
NANO = 'nano'
PETA = 'peta'
PICO = 'pico'
TERA = 'tera'
YOCTO = 'yocto'
YOTTA = 'yotta'
ZEPTO = 'zepto'
ZETTA = 'zetta'

org.accellera.ipxact.v1685_2022.module_parameter_type_resolve module

class org.accellera.ipxact.v1685_2022.module_parameter_type_resolve.ModuleParameterTypeResolve(*values)

Bases: Enum

Determines how a parameter is resolved.

User means the value must be obtained from the user. Generated means the value will be provided by a generator.

Variables:

  • IMMEDIATE – Property content cannot be modified through configuration.

  • USER – Property content can be modified through configuration. Modifications will be saved with the design.

  • GENERATED – Generators may modify this property. Modifications get saved with the design.

GENERATED = 'generated'
IMMEDIATE = 'immediate'
USER = 'user'

org.accellera.ipxact.v1685_2022.module_parameter_type_unit module

class org.accellera.ipxact.v1685_2022.module_parameter_type_unit.ModuleParameterTypeUnit(*values)

Bases: Enum

AMPERE = 'ampere'
CELSIUS = 'Celsius'
COULOMB = 'coulomb'
FARAD = 'farad'
HENRY = 'henry'
HERTZ = 'hertz'
JOULE = 'joule'
KELVIN = 'kelvin'
OHM = 'ohm'
SECOND = 'second'
SIEMENS = 'siemens'
VOLT = 'volt'
WATT = 'watt'

org.accellera.ipxact.v1685_2022.module_parameter_type_usage_type module

class org.accellera.ipxact.v1685_2022.module_parameter_type_usage_type.ModuleParameterTypeUsageType(*values)

Bases: Enum

NONTYPED = 'nontyped'
RUNTIME = 'runtime'
TYPED = 'typed'

org.accellera.ipxact.v1685_2022.monitor_interconnection module

class org.accellera.ipxact.v1685_2022.monitor_interconnection.MonitorInterconnection(name=None, display_name=None, short_description=None, description=None, monitored_active_interface=None, monitor_interface=<factory>, vendor_extensions=None, id=None)

Bases: object

Describes a connection from the interface of one component to any number of monitor interfaces in the design.

An active interface can be connected to unlimited number of monitor interfaces.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • monitored_active_interface – Describes an active interface of the design that all the monitors will be connected to. The componentInterfaceRef and busRef attributes indicate the instance name and bus interface name. The optional path attribute indicates the hierarchical instance name path to the component.

  • monitor_interface – Describes a list of monitor interfaces that are connected to the single active interface. The componentInterfaceRef and busRef attributes indicate the instance name and bus interface name. The optional path attribute indicates the hierarchical instance name path to the component.

  • vendor_extensions

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
id: str | None
monitor_interface: Iterable[MonitorInterfaceType]
monitored_active_interface: MonitorInterfaceType | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.monitor_interface_mode module

class org.accellera.ipxact.v1685_2022.monitor_interface_mode.MonitorInterfaceMode(*values)

Bases: Enum

INITIATOR = 'initiator'
MIRRORED_INITIATOR = 'mirroredInitiator'
MIRRORED_SYSTEM = 'mirroredSystem'
MIRRORED_TARGET = 'mirroredTarget'
SYSTEM = 'system'
TARGET = 'target'

org.accellera.ipxact.v1685_2022.monitor_interface_type module

class org.accellera.ipxact.v1685_2022.monitor_interface_type.MonitorInterfaceType(component_instance_ref=None, bus_ref=None, id=None, description=None, vendor_extensions=None, path=None)

Bases: InterfaceType

Hierarchical reference to an interface being monitored or monitoring another interface.

Variables:

  • description

  • vendor_extensions

  • path – A decending hierarchical (slash separated - example x/y/z) path to the component instance containing the specified component instance in componentInterfaceRef. If not specified the componentInterfaceRef instance shall exist in the current design.

Parameters:

  • component_instance_ref (str | None)

  • bus_ref (str | None)

  • id (str | None)

  • description (Description | None)

  • vendor_extensions (VendorExtensions | None)

  • path (str | None)

bus_ref: str | None
component_instance_ref: str | None
description: Description | None
id: str | None
path: str | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.name_value_pair_type module

class org.accellera.ipxact.v1685_2022.name_value_pair_type.NameValuePairType(name=None, display_name=None, short_description=None, description=None, value=None, vendor_extensions=None, id=None)

Bases: object

Name and value type for use in resolvable elements.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • value

  • vendor_extensions

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
value: Value | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.on_initiator_initiative module

class org.accellera.ipxact.v1685_2022.on_initiator_initiative.OnInitiatorInitiative(*values)

Bases: Enum

BOTH = 'both'
PROVIDES = 'provides'
REQUIRES = 'requires'

org.accellera.ipxact.v1685_2022.on_system_initiative module

class org.accellera.ipxact.v1685_2022.on_system_initiative.OnSystemInitiative(*values)

Bases: Enum

BOTH = 'both'
PROVIDES = 'provides'
REQUIRES = 'requires'

org.accellera.ipxact.v1685_2022.on_target_initiative module

class org.accellera.ipxact.v1685_2022.on_target_initiative.OnTargetInitiative(*values)

Bases: Enum

BOTH = 'both'
PROVIDES = 'provides'
REQUIRES = 'requires'

org.accellera.ipxact.v1685_2022.other_clock_driver module

class org.accellera.ipxact.v1685_2022.other_clock_driver.OtherClockDriver(clock_period=None, clock_pulse_offset=None, clock_pulse_value=None, clock_pulse_duration=None, id=None, clock_name=None, clock_source=None)

Bases: ClockDriverType

Describes a clock not directly associated with an input port.

The clockSource attribute can be used on these clocks to indicate the actual clock source (e.g. an output port of a clock generator cell).

Variables:

  • clock_name – Indicates the name of the clock.

  • clock_source – Indicates the name of the actual clock source (e.g. an output pin of a clock generator cell).

Parameters:
class ClockPeriod(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[float] = None, maximum: Optional[float] = None, units: org.accellera.ipxact.v1685_2022.delay_value_unit_type.DelayValueUnitType = <DelayValueUnitType.NS: 'ns'>)

Bases: RealExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

  • units (DelayValueUnitType)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
units: DelayValueUnitType
value: str
class ClockPulseDuration(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[float] = None, maximum: Optional[float] = None, units: org.accellera.ipxact.v1685_2022.delay_value_unit_type.DelayValueUnitType = <DelayValueUnitType.NS: 'ns'>)

Bases: RealExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

  • units (DelayValueUnitType)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
units: DelayValueUnitType
value: str
class ClockPulseOffset(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[float] = None, maximum: Optional[float] = None, units: org.accellera.ipxact.v1685_2022.delay_value_unit_type.DelayValueUnitType = <DelayValueUnitType.NS: 'ns'>)

Bases: RealExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

  • units (DelayValueUnitType)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
units: DelayValueUnitType
value: str
clock_name: str | None
clock_period: 'ClockDriverType.ClockPeriod' | None
clock_pulse_duration: 'ClockDriverType.ClockPulseDuration' | None
clock_pulse_offset: 'ClockDriverType.ClockPulseOffset' | None
clock_pulse_value: UnsignedBitExpression | None
clock_source: str | None
id: str | None

org.accellera.ipxact.v1685_2022.other_clocks module

class org.accellera.ipxact.v1685_2022.other_clocks.OtherClocks(other_clock_driver=<factory>)

Bases: object

List of clocks associated with the component that are not associated with ports.

Set the clockSource attribute on the clockDriver to indicate the source of a clock not associated with a particular component port.

Parameters:

other_clock_driver (Iterable[OtherClockDriver])

other_clock_driver: Iterable[OtherClockDriver]

org.accellera.ipxact.v1685_2022.packets module

class org.accellera.ipxact.v1685_2022.packets.Packets(packet: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.port_packet_type.PortPacketType] = <factory>)

Bases: PortPacketsType

Parameters:

packet (Iterable[PortPacketType])

packet: Iterable[PortPacketType]

org.accellera.ipxact.v1685_2022.parameter module

class org.accellera.ipxact.v1685_2022.parameter.Parameter(name=None, display_name=None, short_description=None, description=None, vectors=None, arrays=None, value=None, vendor_extensions=None, id=None, parameter_id=None, prompt=None, choice_ref=None, order=None, config_groups=<factory>, minimum=None, maximum=None, type_value=FormatType.STRING, sign=None, prefix=None, unit=None, resolve=ParameterTypeResolve.IMMEDIATE, other_attributes=<factory>)

Bases: ParameterType

A name value pair.

The name is specified by the name element. The value is in the text content of the value element. This value element supports all configurability attributes.

Parameters:
arrays: ConfigurableArrays | None
choice_ref: str | None
config_groups: Iterable[str]
description: Description | None
display_name: DisplayName | None
id: str | None
maximum: str | None
minimum: str | None
name: str | None
order: float | None
other_attributes: Mapping[str, str]
parameter_id: str | None
prefix: ParameterTypePrefix | None
prompt: str | None
resolve: ParameterTypeResolve
short_description: ShortDescription | None
sign: SignType | None
type_value: FormatType
unit: ParameterTypeUnit | None
value: Value | None
vectors: Vectors | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.parameter_type module

class org.accellera.ipxact.v1685_2022.parameter_type.ParameterType(name=None, display_name=None, short_description=None, description=None, vectors=None, arrays=None, value=None, vendor_extensions=None, id=None, parameter_id=None, prompt=None, choice_ref=None, order=None, config_groups=<factory>, minimum=None, maximum=None, type_value=FormatType.STRING, sign=None, prefix=None, unit=None, resolve=ParameterTypeResolve.IMMEDIATE, other_attributes=<factory>)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • vectors

  • arrays

  • value

  • vendor_extensions

  • id

  • parameter_id – ID attribute for uniquely identifying a parameter within its document. Attribute is used to refer to this from a configurable element.

  • prompt – Provides a string used to prompt the user for user- resolved property values.

  • choice_ref – For user defined properties, refers the choice element enumerating the values to choose from.

  • order – For components with auto-generated configuration forms, the user-resolved properties with order attibutes will be presented in ascending order.

  • config_groups – Tags configurable properties so that they may be grouped together. Configurable properties with matching values for this attribute are contained in the same group. The format of this attribute is a string. There is no semantic meaning to this attribute.

  • minimum – For user-resolved properties with numeric values, this indicates the minimum value allowed. Only valid for the types: byte, shortint, int, longint, shortreal and real. The type of this value is the same as the type of the parameter- value, which is specified by the parameter-type attribute.

  • maximum – For user-resolved properties with numeric values, this indicates the maximum value allowed. Only valid for the types: byte, shortint, int, longint, shortreal and real. The type of this value is the same as the type of the parameter- value, which is specified by the parameter-type attribute.

  • type_value – Specifies the type of the value of the parameter. A parameter of type byte is resolved to an 8-bit integer value, shortint is resolved to a 16-bit integer value, int is resolved to a 32-bit integer value, longint is resolved to a 64-bit integer value, shortreal is resolved to a 32-bit floating point value, real is resolved to a 64-bit floating point value, bit is by default resolved to a one bit value, unless a vector size has been specified and the string type is resolved to a string value.

  • sign – Specify the signedness explicitly. The data types byte, shortint, int, longint default to signed. The data type bit defaults to unsigned. When setting this values for the data types string, real and shortreal the setting is ignored.

  • prefix – Defines the prefix that precedes the unit of a value. The prefix is not applied to the value (e.g. in calculations).

  • unit – Defines the unit of the value.

  • resolve – Determines how a property value can be configured.

  • other_attributes

Parameters:
arrays: ConfigurableArrays | None
choice_ref: str | None
config_groups: Iterable[str]
description: Description | None
display_name: DisplayName | None
id: str | None
maximum: str | None
minimum: str | None
name: str | None
order: float | None
other_attributes: Mapping[str, str]
parameter_id: str | None
prefix: ParameterTypePrefix | None
prompt: str | None
resolve: ParameterTypeResolve
short_description: ShortDescription | None
sign: SignType | None
type_value: FormatType
unit: ParameterTypeUnit | None
value: Value | None
vectors: Vectors | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.parameter_type_prefix module

class org.accellera.ipxact.v1685_2022.parameter_type_prefix.ParameterTypePrefix(*values)

Bases: Enum

ATTO = 'atto'
CENTI = 'centi'
DECA = 'deca'
DECI = 'deci'
EXA = 'exa'
FEMTO = 'femto'
GIGA = 'giga'
HECTO = 'hecto'
KILO = 'kilo'
MEGA = 'mega'
MICRO = 'micro'
MILLI = 'milli'
NANO = 'nano'
PETA = 'peta'
PICO = 'pico'
TERA = 'tera'
YOCTO = 'yocto'
YOTTA = 'yotta'
ZEPTO = 'zepto'
ZETTA = 'zetta'

org.accellera.ipxact.v1685_2022.parameter_type_resolve module

class org.accellera.ipxact.v1685_2022.parameter_type_resolve.ParameterTypeResolve(*values)

Bases: Enum

Determines how a parameter is resolved.

User means the value must be obtained from the user. Generated means the value will be provided by a generator.

Variables:

  • IMMEDIATE – Property content cannot be modified through configuration.

  • USER – Property content can be modified through configuration. Modifications will be saved with the design.

  • GENERATED – Generators may modify this property. Modifications get saved with the design.

GENERATED = 'generated'
IMMEDIATE = 'immediate'
USER = 'user'

org.accellera.ipxact.v1685_2022.parameter_type_unit module

class org.accellera.ipxact.v1685_2022.parameter_type_unit.ParameterTypeUnit(*values)

Bases: Enum

AMPERE = 'ampere'
CELSIUS = 'Celsius'
COULOMB = 'coulomb'
FARAD = 'farad'
HENRY = 'henry'
HERTZ = 'hertz'
JOULE = 'joule'
KELVIN = 'kelvin'
OHM = 'ohm'
SECOND = 'second'
SIEMENS = 'siemens'
VOLT = 'volt'
WATT = 'watt'

org.accellera.ipxact.v1685_2022.parameters module

class org.accellera.ipxact.v1685_2022.parameters.Parameters(parameter=<factory>)

Bases: object

A collection of parameters and associated value assertions.

Parameters:

parameter (Iterable[Parameter])

parameter: Iterable[Parameter]

org.accellera.ipxact.v1685_2022.part_select module

class org.accellera.ipxact.v1685_2022.part_select.PartSelect(range=<factory>, indices=None, id=None)

Bases: object

Bit range definition.

Parameters:

  • range (Iterable[Range])

  • indices (Indices | None)

  • id (str | None)

id: str | None
indices: Indices | None
range: Iterable[Range]

org.accellera.ipxact.v1685_2022.path_segment_type module

class org.accellera.ipxact.v1685_2022.path_segment_type.PathSegmentType(value='', other_attributes=<factory>, id=None)

Bases: UnresolvedStringExpression

Identifies one level of hierarchy in the view specifed by viewNameRef.

This is a simple name and optionally some indices into a multi dimensional element.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • id (str | None)

id: str | None
other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.payload module

class org.accellera.ipxact.v1685_2022.payload.Payload(name=None, type_value=None, extension=None, vendor_extensions=None)

Bases: object

Defines the structure of data transported by this port.

Variables:

  • name – Defines the name of the payload. For example: TLM2 or TLM1

  • type_value – Defines the type of the payload.

  • extension – Defines the name of the payload extension. If attribute is not specified, it is by default optional.

  • vendor_extensions

Parameters:
class Extension(value='', mandatory=False)

Bases: object

Variables:

  • value

  • mandatory – True if the payload extension is mandatory.

Parameters:

  • value (str)

  • mandatory (bool)

mandatory: bool
value: str
extension: Extension | None
name: str | None
type_value: PayloadType | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.payload_type module

class org.accellera.ipxact.v1685_2022.payload_type.PayloadType(*values)

Bases: Enum

GENERIC = 'generic'
SPECIFIC = 'specific'

org.accellera.ipxact.v1685_2022.phase module

class org.accellera.ipxact.v1685_2022.phase.Phase(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: RealExpression

This is an non-negative floating point number that is used to sequence when a generator is run.

The generators are run in order starting with zero. There may be multiple generators with the same phase number. In this case, the order should not matter with respect to other generators at the same phase. If no phase number is given the generator will be considered in the “last” phase and these generators will be run in the order in which they are encountered while processing generator elements.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.port module

class org.accellera.ipxact.v1685_2022.port.Port(name=None, display_name=None, short_description=None, description=None, wire=None, transactional=None, structured=None, field_maps=None, arrays=None, access=None, parameters=None, vendor_extensions=None, id=None)

Bases: PortType

Describes port characteristics.

Parameters:
access: PortAccessType1 | None
arrays: Arrays | None
description: Description | None
display_name: DisplayName | None
field_maps: FieldMaps | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
structured: PortStructuredType | None
transactional: PortTransactionalType | None
vendor_extensions: VendorExtensions | None
wire: PortWireType | None

org.accellera.ipxact.v1685_2022.port_access_handle module

class org.accellera.ipxact.v1685_2022.port_access_handle.PortAccessHandle(view_ref=<factory>, indices=None, slices=None, vendor_extensions=None, force=True, id=None)

Bases: object

Variables:

  • view_ref – A list of views this accessHandle is applicable to. Note this element is optional, if it is not present the accessHandle applies to all views.

  • indices – For a multi dimensional IP-XACT object, indices can be specified to select the element the accessHandle applies to. This is an index into a multi-dimensional array and follows C-semantics for indexing.

  • slices

  • vendor_extensions

  • force

  • id

Parameters:
class Indices(index=<factory>)

Bases: object

Variables:

index – An index into the IP-XACT object.

Parameters:

index (Iterable[Index])

class Index(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[int] = None, maximum: Optional[int] = None, id: Optional[str] = None)

Bases: UnsignedIntExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

  • id (str | None)

id: str | None
maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str
index: Iterable[Index]
class ViewRef(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
force: bool
id: str | None
indices: Indices | None
slices: PortSlicesType | None
vendor_extensions: VendorExtensions | None
view_ref: Iterable[ViewRef]

org.accellera.ipxact.v1685_2022.port_access_type module

class org.accellera.ipxact.v1685_2022.port_access_type.PortAccessType(value=None)

Bases: object

Indicates how a netlister accesses a port.

‘ref’ means accessed by reference (default) and ‘ptr’ means accessed by pointer.

Parameters:

value (SimplePortAccessType | None)

value: SimplePortAccessType | None

org.accellera.ipxact.v1685_2022.port_access_type_1 module

class org.accellera.ipxact.v1685_2022.port_access_type_1.PortAccessType1(port_access_type=None, access_handles=None)

Bases: object

Variables:

  • port_access_type – Indicates how a netlister accesses a port. ‘ref’ means accessed by reference (default) and ‘ptr’ means accessed through a pointer.

  • access_handles

Parameters:

  • port_access_type (PortAccessType | None)

  • access_handles (AccessHandles | None)

access_handles: AccessHandles | None
port_access_type: PortAccessType | None

org.accellera.ipxact.v1685_2022.port_packet_field_type module

class org.accellera.ipxact.v1685_2022.port_packet_field_type.PortPacketFieldType(name=None, display_name=None, short_description=None, description=None, width=None, value=None, endianness=None, qualifier=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • width

  • value

  • endianness

  • qualifier – The type of information this port carries a wire port can carry both address and data, but may not mix this with a clock or reset.

  • vendor_extensions

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
endianness: EndianessType | None
id: str | None
name: str | None
qualifier: QualifierType | None
short_description: ShortDescription | None
value: UnsignedBitVectorExpression | None
vendor_extensions: VendorExtensions | None
width: UnresolvedUnsignedPositiveIntExpression | None

org.accellera.ipxact.v1685_2022.port_packet_fields_type module

class org.accellera.ipxact.v1685_2022.port_packet_fields_type.PortPacketFieldsType(packet_field: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.port_packet_field_type.PortPacketFieldType] = <factory>)

Bases: object

Parameters:

packet_field (Iterable[PortPacketFieldType])

packet_field: Iterable[PortPacketFieldType]

org.accellera.ipxact.v1685_2022.port_packet_type module

class org.accellera.ipxact.v1685_2022.port_packet_type.PortPacketType(name=None, display_name=None, short_description=None, description=None, endianness=None, packet_fields=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • endianness

  • packet_fields

  • vendor_extensions

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
endianness: EndianessType | None
id: str | None
name: str | None
packet_fields: PortPacketFieldsType | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.port_packets_type module

class org.accellera.ipxact.v1685_2022.port_packets_type.PortPacketsType(packet: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.port_packet_type.PortPacketType] = <factory>)

Bases: object

Parameters:

packet (Iterable[PortPacketType])

packet: Iterable[PortPacketType]

org.accellera.ipxact.v1685_2022.port_path_segment_type module

class org.accellera.ipxact.v1685_2022.port_path_segment_type.PortPathSegmentType(value='', other_attributes=<factory>, id=None)

Bases: StringExpression

Identifies one level of hierarchy in the view specifed by viewNameRef.

This is a simple name and optionally some indices into a multi dimensional element.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • id (str | None)

id: str | None
other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.port_slice_type module

class org.accellera.ipxact.v1685_2022.port_slice_type.PortSliceType(path_segments=None, range=None, id=None)

Bases: object

Contains the HDL path information for a slice of the IP-XACT object.

Variables:

  • path_segments – An ordered list of pathSegment elements. When concatenated with a desired separator the elements in this form a HDL path for the parent slice into the referenced view.

  • range – A range to be applied to the concatenation of the above path segments

  • id

Parameters:
class PathSegments(path_segment: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.port_path_segment_type.PortPathSegmentType] = <factory>)

Bases: object

Parameters:

path_segment (Iterable[PortPathSegmentType])

path_segment: Iterable[PortPathSegmentType]
id: str | None
path_segments: PathSegments | None
range: Range | None

org.accellera.ipxact.v1685_2022.port_slices_type module

class org.accellera.ipxact.v1685_2022.port_slices_type.PortSlicesType(slice=<factory>)

Bases: object

Each slice specifies the HDL path for part of the parent IP-XACT object.

The slices must be concatenated to calculate the entire path. If there is only one slice, it is assumed to be the path for the entire IP-XACT object.

Variables:

slice – The HDL path for a slice of the IP-XACT object.

Parameters:

slice (Iterable[PortSliceType])

slice: Iterable[PortSliceType]

org.accellera.ipxact.v1685_2022.port_transactional_type module

class org.accellera.ipxact.v1685_2022.port_transactional_type.PortTransactionalType(initiative=None, kind=None, bus_width=None, qualifier=None, protocol=None, trans_type_defs=None, connection=None, power_constraints=None, all_logical_initiatives_allowed=False)

Bases: object

Transactional port type.

Variables:

  • initiative – Defines how the port accesses this service.

  • kind – Define the kind of transactional port

  • bus_width – Defines the bus width in bits.This can be the result of an expression.

  • qualifier – The type of information this port carries A transactional port can carry both address and data information.

  • protocol – Defines the protocol type. Defaults to tlm_base_protocol_type for TLM sockets

  • trans_type_defs – Definition of the port type expressed in the default language for this port (i.e. SystemC or SystemV).

  • connection – Bounds number of legal connections.

  • power_constraints – Wire port power constraints.

  • all_logical_initiatives_allowed – True if logical ports with different initiatives from the physical port initiative may be mapped onto this port. Forbidden for phantom ports, which always allow logical ports with all initiatives value to be mapped onto the physical port. Also ignored for “both” ports, since any logical port may be mapped to a physical “both” port.

Parameters:
class Connection(max_connections=None, min_connections=None)

Bases: object

Variables:

  • max_connections – Indicates the maximum number of connections this port supports. If this element is not present or set to 0 it implies an unbounded number of allowed connections.

  • min_connections – Indicates the minimum number of connections this port supports. If this element is not present, the minimum number of allowed connections is 1.

Parameters:
max_connections: UnsignedIntExpression | None
min_connections: UnsignedIntExpression | None
class PowerConstraints(power_constraint=<factory>)

Bases: object

Variables:

power_constraint – Single wire port set of power constraints.

Parameters:

power_constraint (Iterable[TransactionalPowerConstraintType])

power_constraint: Iterable[TransactionalPowerConstraintType]
all_logical_initiatives_allowed: bool
bus_width: BusWidth | None
connection: Connection | None
initiative: Initiative | None
kind: Kind | None
power_constraints: PowerConstraints | None
protocol: Protocol | None
qualifier: QualifierType | None
trans_type_defs: TransTypeDefs | None

org.accellera.ipxact.v1685_2022.port_type module

class org.accellera.ipxact.v1685_2022.port_type.PortType(name=None, display_name=None, short_description=None, description=None, wire=None, transactional=None, structured=None, field_maps=None, arrays=None, access=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

A port description, giving a name and an access type for high level ports.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • wire – Defines a port whose type resolves to simple bits.

  • transactional – Defines a port that implements or uses a service that can be implemented with functions or methods.

  • structured – Represents a port that has subport structure.

  • field_maps

  • arrays

  • access – Port access characteristics.

  • parameters

  • vendor_extensions

  • id

Parameters:
access: PortAccessType1 | None
arrays: Arrays | None
description: Description | None
display_name: DisplayName | None
field_maps: FieldMaps | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
structured: PortStructuredType | None
transactional: PortTransactionalType | None
vendor_extensions: VendorExtensions | None
wire: PortWireType | None

org.accellera.ipxact.v1685_2022.port_wire_type module

class org.accellera.ipxact.v1685_2022.port_wire_type.PortWireType(direction=None, qualifier=None, vectors=None, wire_type_defs=None, domain_type_defs=None, signal_type_defs=None, drivers=None, constraint_sets=None, power_constraints=None, all_logical_directions_allowed=False)

Bases: object

Wire port type for a component.

Variables:

  • direction – The direction of a wire style port. The basic directions for a port are ‘in’ for input ports, ‘out’ for output port and ‘inout’ for bidirectional and tristate ports. A value of ‘phantom’ is also allowed and define a port that exist on the IP-XACT component but not on the HDL model.

  • qualifier – The type of information this port carries a wire port can carry both address and data, but may not mix this with a clock or reset.

  • vectors – Vectored information.

  • wire_type_defs

  • domain_type_defs

  • signal_type_defs

  • drivers

  • constraint_sets

  • power_constraints – Wire port power constraints.

  • all_logical_directions_allowed – True if logical ports with different directions from the physical port direction may be mapped onto this port. Forbidden for phantom ports, which always allow logical ports with all direction value to be mapped onto the physical port. Also ignored for inout ports, since any logical port maybe mapped to a physical inout port.

Parameters:
class PowerConstraints(power_constraint=<factory>)

Bases: object

Variables:

power_constraint – Single wire port set of power constraints.

Parameters:

power_constraint (Iterable[WirePowerConstraintType])

power_constraint: Iterable[WirePowerConstraintType]
all_logical_directions_allowed: bool
constraint_sets: ConstraintSets | None
direction: ComponentPortDirectionType | None
domain_type_defs: DomainTypeDefs | None
drivers: Drivers | None
power_constraints: PowerConstraints | None
qualifier: QualifierType | None
signal_type_defs: SignalTypeDefs | None
vectors: ExtendedVectorsType | None
wire_type_defs: WireTypeDefs | None

org.accellera.ipxact.v1685_2022.power_domain_ref module

class org.accellera.ipxact.v1685_2022.power_domain_ref.PowerDomainRef(value='')

Bases: object

Power domain.

It is the user’s responsibility to ensure it matches an existing power domain in UPF/CPF file.

Parameters:

value (str)

value: str

org.accellera.ipxact.v1685_2022.presence module

class org.accellera.ipxact.v1685_2022.presence.Presence(value=PresenceType.OPTIONAL)

Bases: object

If this element is present, the existance of the port is controlled by the specified value.

valid values are ‘illegal’, ‘required’ and ‘optional’.

Parameters:

value (PresenceType)

value: PresenceType

org.accellera.ipxact.v1685_2022.presence_type module

class org.accellera.ipxact.v1685_2022.presence_type.PresenceType(*values)

Bases: Enum

ILLEGAL = 'illegal'
OPTIONAL = 'optional'
REQUIRED = 'required'

org.accellera.ipxact.v1685_2022.protocol module

class org.accellera.ipxact.v1685_2022.protocol.Protocol(protocol_type=None, payload=None)

Bases: object

Defines the protocol type.

Defaults to tlm_base_protocol_type for TLM sockets

Parameters:
class ProtocolType(value: org.accellera.ipxact.v1685_2022.protocol_type_type.ProtocolTypeType | None = None, custom: str | None = None)

Bases: object

Parameters:
custom: str | None
value: ProtocolTypeType | None
payload: Payload | None
protocol_type: ProtocolType | None

org.accellera.ipxact.v1685_2022.protocol_type_type module

class org.accellera.ipxact.v1685_2022.protocol_type_type.ProtocolTypeType(*values)

Bases: Enum

CUSTOM = 'custom'
TLM = 'tlm'

org.accellera.ipxact.v1685_2022.qualified_expression module

class org.accellera.ipxact.v1685_2022.qualified_expression.QualifiedExpression(value='', other_attributes=<factory>)

Bases: ComplexBaseExpression

Represents an expression qualified by an accompanying type.

It supports an expression value.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.qualifier_type module

class org.accellera.ipxact.v1685_2022.qualifier_type.QualifierType(is_address=None, is_data=None, is_clock=None, is_reset=None, is_valid=None, is_interrupt=None, is_clock_en=None, is_power_en=None, is_opcode=None, is_protection=None, is_flow_control=None, is_user=None, is_request=None, is_response=None, id=None)

Bases: object

Variables:

  • is_address – If this element is present, the port contains address information.

  • is_data – If this element is present, the port contains data information.

  • is_clock – If this element is present, the port contains only clock information.

  • is_reset – If this element is present, the port contains only reset information.

  • is_valid – If this element is present, the port signifies that the data on the interface is currently valid

  • is_interrupt – If this element is present, the port contains only interrupt information.

  • is_clock_en – If this element is present, the port indicates that an associated conditional clock should be turned on.

  • is_power_en – If this element is present, the port indicates that an associated power domain should be activated.

  • is_opcode – If this element is present, the port determines the interpretation of other signals in the interface.

  • is_protection – If this element is present, the port implements a protection signal.

  • is_flow_control – If this element is present, the port is used by the interface’s flow control mechanism.

  • is_user – If this element is present, the port is used for user defined behavior.

  • is_request – If this element is present, the port implements a request signal.

  • is_response – If this element is present, the port implements a response signal.

  • id

Parameters:

  • is_address (bool | None)

  • is_data (bool | None)

  • is_clock (bool | None)

  • is_reset (IsReset | None)

  • is_valid (bool | None)

  • is_interrupt (bool | None)

  • is_clock_en (IsClockEn | None)

  • is_power_en (IsPowerEn | None)

  • is_opcode (bool | None)

  • is_protection (bool | None)

  • is_flow_control (IsFlowControl | None)

  • is_user (IsUser | None)

  • is_request (bool | None)

  • is_response (bool | None)

  • id (str | None)

class IsClockEn(value=None, level=None)

Bases: object

Variables:

  • value

  • level – Assertion level

Parameters:
level: IsClockEnLevel | None
value: bool | None
class IsFlowControl(value=None, flow_type=None, user=None)

Bases: object

Variables:

  • value

  • flow_type – Controlled flow type

  • user – User flow type information

Parameters:
flow_type: IsFlowControlFlowType | None
user: str | None
value: bool | None
class IsPowerEn(value=None, level=None, power_domain_ref=None)

Bases: object

Variables:

  • value

  • level – Assertion level

  • power_domain_ref – PowerDomain references

Parameters:

  • value (bool | None)

  • level (IsPowerEnLevel | None)

  • power_domain_ref (str | None)

level: IsPowerEnLevel | None
power_domain_ref: str | None
value: bool | None
class IsReset(value=None, level=None)

Bases: object

Variables:

  • value

  • level – Assertion level

Parameters:
level: IsResetLevel | None
value: bool | None
class IsUser(value=None, user=None)

Bases: object

Variables:

  • value

  • user – User behaviour

Parameters:

  • value (bool | None)

  • user (str | None)

user: str | None
value: bool | None
id: str | None
is_address: bool | None
is_clock: bool | None
is_clock_en: IsClockEn | None
is_data: bool | None
is_flow_control: IsFlowControl | None
is_interrupt: bool | None
is_opcode: bool | None
is_power_en: IsPowerEn | None
is_protection: bool | None
is_request: bool | None
is_reset: IsReset | None
is_response: bool | None
is_user: IsUser | None
is_valid: bool | None

org.accellera.ipxact.v1685_2022.range module

class org.accellera.ipxact.v1685_2022.range.Range(left=None, right=None)

Bases: object

Left and right bound of a reference into a vector.

Parameters:
left: Left | None
right: Right | None

org.accellera.ipxact.v1685_2022.read_action module

class org.accellera.ipxact.v1685_2022.read_action.ReadAction(value=None, modify=None)

Bases: object

A list of possible actions for a read to set the field after the read.

‘clear’ means that after a read the field is cleared. ‘set’ means that after a read the field is set. ‘modify’ means after a read the field is modified. If not present the field value is not modified after a read.

Parameters:
modify: str | None
value: ReadActionType | None

org.accellera.ipxact.v1685_2022.read_action_type module

class org.accellera.ipxact.v1685_2022.read_action_type.ReadActionType(*values)

Bases: Enum

CLEAR = 'clear'
MODIFY = 'modify'
SET = 'set'

org.accellera.ipxact.v1685_2022.read_response module

class org.accellera.ipxact.v1685_2022.read_response.ReadResponse(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>)

Bases: UnsignedBitVectorExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.real_expression module

class org.accellera.ipxact.v1685_2022.real_expression.RealExpression(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: ComplexBaseExpression

A real which supports an expression value.

Variables:

  • minimum – For elements which can be specified using expression which are supposed to be resolved to a real value, this indicates the minimum value allowed.

  • maximum – For elements which can be specified using expression which are supposed to be resolved to a real value, this indicates the maximum value allowed.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.register_definitions module

class org.accellera.ipxact.v1685_2022.register_definitions.RegisterDefinitions(register_definition: collections.abc.Iterable['RegisterDefinitions.RegisterDefinition'] = <factory>)

Bases: object

Parameters:

register_definition (Iterable[RegisterDefinition])

class RegisterDefinition(name=None, display_name=None, short_description=None, description=None, type_identifier=None, size=None, volatile=None, access_policies=None, field_value=<factory>, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • type_identifier – Identifier name used to indicate that multiple register elements contain the exact same information for the elements in the registerDefinitionGroup.

  • size – Width of the register in bits.

  • volatile

  • access_policies

  • field_value – Describes individual bit fields within the register.

  • vendor_extensions

  • id

Parameters:
access_policies: AccessPolicies | None
description: Description | None
display_name: DisplayName | None
field_value: Iterable[FieldType]
id: str | None
name: str | None
short_description: ShortDescription | None
size: UnsignedPositiveIntExpression | None
type_identifier: str | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
register_definition: Iterable[RegisterDefinition]

org.accellera.ipxact.v1685_2022.register_file module

class org.accellera.ipxact.v1685_2022.register_file.RegisterFile(name=None, display_name=None, short_description=None, description=None, access_handles=None, array=None, address_offset=None, register_file_definition_ref=None, type_identifier=None, range=None, access_policies=None, register=<factory>, register_file=<factory>, parameters=None, vendor_extensions=None, id=None)

Bases: object

A structure of registers and register files.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • array

  • address_offset – Offset from the address block’s baseAddress or the containing register file’s addressOffset, expressed as the number of addressUnitBits from the containing memoryMap or localMemoryMap.

  • register_file_definition_ref

  • type_identifier – Identifier name used to indicate that multiple registerFile elements contain the exact same information except for the elements in the registerFileInstanceGroup.

  • range – The range of a register file. Expressed as the number of addressable units accessible to the block. Specified in units of addressUnitBits.

  • access_policies

  • register – A single register

  • register_file – A structure of registers and register files

  • parameters

  • vendor_extensions

  • id

Parameters:
class Register(name=None, display_name=None, short_description=None, description=None, access_handles=None, array=None, address_offset=None, register_definition_ref=None, type_identifier=None, size=None, volatile=None, access_policies=None, field_value=<factory>, alternate_registers=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • array

  • address_offset – Offset from the address block’s baseAddress or the containing register file’s addressOffset, expressed as the number of addressUnitBits from the containing memoryMap or localMemoryMap.

  • register_definition_ref

  • type_identifier – Identifier name used to indicate that multiple register elements contain the exact same information for the elements in the registerDefinitionGroup.

  • size – Width of the register in bits.

  • volatile

  • access_policies

  • field_value – Describes individual bit fields within the register.

  • alternate_registers

  • parameters

  • vendor_extensions

  • id

Parameters:
class RegisterDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_offset: UnsignedLongintExpression | None
alternate_registers: AlternateRegisters | None
array: Array | None
description: Description | None
display_name: DisplayName | None
field_value: Iterable[FieldType]
id: str | None
name: str | None
parameters: Parameters | None
register_definition_ref: RegisterDefinitionRef | None
short_description: ShortDescription | None
size: UnsignedPositiveIntExpression | None
type_identifier: str | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
class RegisterFileDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_offset: UnsignedLongintExpression | None
array: Array | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
range: UnsignedPositiveLongintExpression | None
register: Iterable[Register]
register_file: Iterable[RegisterFile]
register_file_definition_ref: RegisterFileDefinitionRef | None
short_description: ShortDescription | None
type_identifier: str | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.register_file_definitions module

class org.accellera.ipxact.v1685_2022.register_file_definitions.RegisterFileDefinitions(register_file_definition: collections.abc.Iterable['RegisterFileDefinitions.RegisterFileDefinition'] = <factory>)

Bases: object

Parameters:

register_file_definition (Iterable[RegisterFileDefinition])

class RegisterFileDefinition(name=None, display_name=None, short_description=None, description=None, type_identifier=None, range=None, access_policies=None, register=<factory>, register_file=<factory>, address_unit_bits=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • type_identifier – Identifier name used to indicate that multiple registerFile elements contain the exact same information except for the elements in the registerFileInstanceGroup.

  • range – The range of a register file. Expressed as the number of addressable units accessible to the block. Specified in units of addressUnitBits.

  • access_policies

  • register – A single register

  • register_file – A structure of registers and register files

  • address_unit_bits

  • vendor_extensions

  • id

Parameters:
class Register(name=None, display_name=None, short_description=None, description=None, access_handles=None, array=None, address_offset=None, register_definition_ref=None, type_identifier=None, size=None, volatile=None, access_policies=None, field_value=<factory>, alternate_registers=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • array

  • address_offset – Offset from the address block’s baseAddress or the containing register file’s addressOffset, expressed as the number of addressUnitBits from the containing memoryMap or localMemoryMap.

  • register_definition_ref

  • type_identifier – Identifier name used to indicate that multiple register elements contain the exact same information for the elements in the registerDefinitionGroup.

  • size – Width of the register in bits.

  • volatile

  • access_policies

  • field_value – Describes individual bit fields within the register.

  • alternate_registers

  • parameters

  • vendor_extensions

  • id

Parameters:
class RegisterDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_offset: UnsignedLongintExpression | None
alternate_registers: AlternateRegisters | None
array: Array | None
description: Description | None
display_name: DisplayName | None
field_value: Iterable[FieldType]
id: str | None
name: str | None
parameters: Parameters | None
register_definition_ref: RegisterDefinitionRef | None
short_description: ShortDescription | None
size: UnsignedPositiveIntExpression | None
type_identifier: str | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
access_policies: AccessPolicies | None
address_unit_bits: AddressUnitBits | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
range: UnsignedPositiveLongintExpression | None
register: Iterable[Register]
register_file: Iterable[RegisterFile]
short_description: ShortDescription | None
type_identifier: str | None
vendor_extensions: VendorExtensions | None
register_file_definition: Iterable[RegisterFileDefinition]

org.accellera.ipxact.v1685_2022.register_file_ref module

class org.accellera.ipxact.v1685_2022.register_file_ref.RegisterFileRef(indices: org.accellera.ipxact.v1685_2022.indices.Indices | None = None, register_file_ref: str | None = None, id: str | None = None)

Bases: object

Parameters:

  • indices (Indices | None)

  • register_file_ref (str | None)

  • id (str | None)

id: str | None
indices: Indices | None
register_file_ref: str | None

org.accellera.ipxact.v1685_2022.register_ref module

class org.accellera.ipxact.v1685_2022.register_ref.RegisterRef(indices: org.accellera.ipxact.v1685_2022.indices.Indices | None = None, register_ref: str | None = None)

Bases: object

Parameters:

  • indices (Indices | None)

  • register_ref (str | None)

indices: Indices | None
register_ref: str | None

org.accellera.ipxact.v1685_2022.requires_driver module

class org.accellera.ipxact.v1685_2022.requires_driver.RequiresDriver(value=False, driver_type=RequiresDriverDriverType.ANY)

Bases: object

Specifies if a port requires a driver.

Default is false. The attribute driverType can further qualify what type of driver is required. Undefined behaviour if direction is not input or inout. Driver type any indicates that any unspecified type of driver must be connected

Variables:

  • value

  • driver_type – Defines the type of driver that is required. The default is any type of driver. The 2 other options are a clock type driver or a singleshot type driver.

Parameters:
driver_type: RequiresDriverDriverType
value: bool

org.accellera.ipxact.v1685_2022.requires_driver_driver_type module

class org.accellera.ipxact.v1685_2022.requires_driver_driver_type.RequiresDriverDriverType(*values)

Bases: Enum

ANY = 'any'
CLOCK = 'clock'
SINGLE_SHOT = 'singleShot'

org.accellera.ipxact.v1685_2022.reset module

class org.accellera.ipxact.v1685_2022.reset.Reset(value=None, mask=None, reset_type_ref=None, id=None)

Bases: object

Register value at reset.

Variables:

  • value – The value itself.

  • mask – Mask to be anded with the value before comparing to the reset value.

  • reset_type_ref – Reference to a user defined resetType. Assumed to be HARD if not present.

  • id

Parameters:
id: str | None
mask: UnsignedBitVectorExpression | None
reset_type_ref: str | None
value: UnsignedBitVectorExpression | None

org.accellera.ipxact.v1685_2022.return_type_type module

class org.accellera.ipxact.v1685_2022.return_type_type.ReturnTypeType(*values)

Bases: Enum

INT = 'int'
VOID = 'void'

org.accellera.ipxact.v1685_2022.right module

class org.accellera.ipxact.v1685_2022.right.Right(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: UnsignedIntExpression

The optional element right specifies the right boundary.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.shared_type module

class org.accellera.ipxact.v1685_2022.shared_type.SharedType(*values)

Bases: Enum

The sharedness of the memoryMap content.

NO = 'no'
UNDEFINED = 'undefined'
YES = 'yes'

org.accellera.ipxact.v1685_2022.short_description module

class org.accellera.ipxact.v1685_2022.short_description.ShortDescription(value='')

Bases: object

Brief description suitable for titles, software comments and pop-up windows.

Being a SystemVerilog expression the text can be constructed using parameters, e.g, by concatentation or $sformatf().

Parameters:

value (str)

value: str

org.accellera.ipxact.v1685_2022.sign_type module

class org.accellera.ipxact.v1685_2022.sign_type.SignType(*values)

Bases: Enum

This is an indication of the signedness of the value.

SIGNED = 'signed'
UNSIGNED = 'unsigned'

org.accellera.ipxact.v1685_2022.signal_type_def module

class org.accellera.ipxact.v1685_2022.signal_type_def.SignalTypeDef(signal_type=None, view_ref=<factory>, id=None)

Bases: object

Definition of a single signal type defintion that can relate to multiple views.

Variables:

  • signal_type – defines the signal type for the port. Continuous- conservative is a signal which is continuous in time and quantity, where the quantity represents voltage and current to capture the conservative behavior of an electrical network (i. e. Kirchhoff’s Laws apply), and which has no direction. Continuous-non-conservative is a directed signal which is continuous in time and quantity, where the quantity represents either a voltage or a current (often called signal flow). In this case it only captures the non-conservative behavior of a set of interconnected components. Discrete is a directed sampled signal which is time-discrete and value-continuous (the value may also be quantified), where the value represents either a voltage or a current (other representations are possible also). It captures the non-conservative behavior of a set of interconnected components. Digital is a time-discrete and value- discrete signal. The interpretation of the signal values is described by the wireTypeDefs.

  • view_ref – A reference to a view in the file for which this type applies.

  • id

Parameters:
class ViewRef(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
id: str | None
signal_type: SignalTypeDefSignalType | None
view_ref: Iterable[ViewRef]

org.accellera.ipxact.v1685_2022.signal_type_def_signal_type module

class org.accellera.ipxact.v1685_2022.signal_type_def_signal_type.SignalTypeDefSignalType(*values)

Bases: Enum

CONTINUOUS_CONSERVATIVE = 'continuous-conservative'
CONTINUOUS_NON_CONSERVATIVE = 'continuous-non-conservative'
DIGITAL = 'digital'
DISCRETE = 'discrete'

org.accellera.ipxact.v1685_2022.signal_type_defs module

class org.accellera.ipxact.v1685_2022.signal_type_defs.SignalTypeDefs(signal_type_def=<factory>)

Bases: object

The group of signal type definitions.

Parameters:

signal_type_def (Iterable[SignalTypeDef])

signal_type_def: Iterable[SignalTypeDef]

org.accellera.ipxact.v1685_2022.signed_longint_expression module

class org.accellera.ipxact.v1685_2022.signed_longint_expression.SignedLongintExpression(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: ComplexBaseExpression

An unsigned longint which supports an expression value.

Variables:

  • minimum – For elements which can be specified using expression which are supposed to be resolved to a signed longint value, this indicates the minimum value allowed.

  • maximum – For elements which can be specified using expression which are supposed to be resolved to a signed longint value, this indicates the maximum value allowed.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.simple_access_handle module

class org.accellera.ipxact.v1685_2022.simple_access_handle.SimpleAccessHandle(view_ref=<factory>, path_segments=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • view_ref – A list of views this accessHandle is applicable to. Note this element is optional, if it is not present the accessHandle applies to all views.

  • path_segments – An ordered list of pathSegment elements. When concatenated with a desired separator the elements in this form a HDL path for the parent slice into the referenced view.

  • vendor_extensions

  • id

Parameters:
class PathSegments(path_segment: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.path_segment_type.PathSegmentType] = <factory>)

Bases: object

Parameters:

path_segment (Iterable[PathSegmentType])

path_segment: Iterable[PathSegmentType]
class ViewRef(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
id: str | None
path_segments: PathSegments | None
vendor_extensions: VendorExtensions | None
view_ref: Iterable[ViewRef]

org.accellera.ipxact.v1685_2022.simple_clearbox_type module

class org.accellera.ipxact.v1685_2022.simple_clearbox_type.SimpleClearboxType(*values)

Bases: Enum

INTERFACE = 'interface'
PIN = 'pin'
SIGNAL = 'signal'

org.accellera.ipxact.v1685_2022.simple_file_type module

class org.accellera.ipxact.v1685_2022.simple_file_type.SimpleFileType(*values)

Bases: Enum

ASM_SOURCE = 'asmSource'
CPP_SOURCE = 'cppSource'
C_SOURCE = 'cSource'
EXECUTABLE_HDL = 'executableHdl'
E_SOURCE = 'eSource'
LIBERTY_SOURCE = 'libertySource'
OVASOURCE = 'OVASource'
PERL_SOURCE = 'perlSource'
PSL_SOURCE = 'pslSource'
SDC = 'SDC'
SPICE_SOURCE = 'spiceSource'
SVASOURCE = 'SVASource'
SW_OBJECT = 'swObject'
SW_OBJECT_LIBRARY = 'swObjectLibrary'
SYSTEM_CAMS_SOURCE = 'systemCAmsSource'
SYSTEM_CBINARY_LIBRARY = 'systemCBinaryLibrary'
SYSTEM_CSOURCE = 'systemCSource'
SYSTEM_CSOURCE_2_0 = 'systemCSource-2.0'
SYSTEM_CSOURCE_2_0_1 = 'systemCSource-2.0.1'
SYSTEM_CSOURCE_2_1 = 'systemCSource-2.1'
SYSTEM_CSOURCE_2_2 = 'systemCSource-2.2'
SYSTEM_CSOURCE_2_3 = 'systemCSource-2.3'
SYSTEM_RDL = 'systemRDL'
SYSTEM_RDL_1_0 = 'systemRDL-1.0'
SYSTEM_RDL_2_0 = 'systemRDL-2.0'
SYSTEM_VERILOG_SOURCE = 'systemVerilogSource'
SYSTEM_VERILOG_SOURCE_2009 = 'systemVerilogSource-2009'
SYSTEM_VERILOG_SOURCE_2012 = 'systemVerilogSource-2012'
SYSTEM_VERILOG_SOURCE_2017 = 'systemVerilogSource-2017'
SYSTEM_VERILOG_SOURCE_3_0 = 'systemVerilogSource-3.0'
SYSTEM_VERILOG_SOURCE_3_1 = 'systemVerilogSource-3.1'
SYSTEM_VERILOG_SOURCE_3_1A = 'systemVerilogSource-3.1a'
TCL_SOURCE = 'tclSource'
UNELABORATED_HDL = 'unelaboratedHdl'
UNKNOWN = 'unknown'
USER = 'user'
VERA_SOURCE = 'veraSource'
VERILOG_AMS_SOURCE = 'verilogAmsSource'
VERILOG_BINARY_LIBRARY = 'verilogBinaryLibrary'
VERILOG_SOURCE = 'verilogSource'
VERILOG_SOURCE_2001 = 'verilogSource-2001'
VERILOG_SOURCE_2005 = 'verilogSource-2005'
VERILOG_SOURCE_95 = 'verilogSource-95'
VHDL_AMS_SOURCE = 'vhdlAmsSource'
VHDL_BINARY_LIBRARY = 'vhdlBinaryLibrary'
VHDL_SOURCE = 'vhdlSource'
VHDL_SOURCE_2002 = 'vhdlSource-2002'
VHDL_SOURCE_2008 = 'vhdlSource-2008'
VHDL_SOURCE_87 = 'vhdlSource-87'
VHDL_SOURCE_93 = 'vhdlSource-93'

org.accellera.ipxact.v1685_2022.simple_port_access_type module

class org.accellera.ipxact.v1685_2022.simple_port_access_type.SimplePortAccessType(*values)

Bases: Enum

PTR = 'ptr'
REF = 'ref'

org.accellera.ipxact.v1685_2022.single_shot_driver module

class org.accellera.ipxact.v1685_2022.single_shot_driver.SingleShotDriver(single_shot_offset=None, single_shot_value=None, single_shot_duration=None)

Bases: object

Describes a driven one-shot port.

Variables:

  • single_shot_offset – Time in nanoseconds until start of one- shot.

  • single_shot_value – Value of port after first edge of one- shot.

  • single_shot_duration – Duration in nanoseconds of the one shot.

Parameters:
class SingleShotDuration(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[float] = None, maximum: Optional[float] = None, units: org.accellera.ipxact.v1685_2022.delay_value_unit_type.DelayValueUnitType = <DelayValueUnitType.NS: 'ns'>)

Bases: RealExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

  • units (DelayValueUnitType)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
units: DelayValueUnitType
value: str
class SingleShotOffset(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[float] = None, maximum: Optional[float] = None, units: org.accellera.ipxact.v1685_2022.delay_value_unit_type.DelayValueUnitType = <DelayValueUnitType.NS: 'ns'>)

Bases: RealExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

  • units (DelayValueUnitType)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
units: DelayValueUnitType
value: str
single_shot_duration: SingleShotDuration | None
single_shot_offset: SingleShotOffset | None
single_shot_value: UnsignedBitVectorExpression | None

org.accellera.ipxact.v1685_2022.slice_type module

class org.accellera.ipxact.v1685_2022.slice_type.SliceType(path_segments=None, range=None, id=None)

Bases: object

Contains the HDL path information for a slice of the IP-XACT object.

Variables:

  • path_segments – An ordered list of pathSegment elements. When concatenated with a desired separator the elements in this form a HDL path for the parent slice into the referenced view.

  • range – A range to be applied to the concatenation of the above path segments

  • id

Parameters:
class PathSegments(path_segment: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.path_segment_type.PathSegmentType] = <factory>)

Bases: object

Parameters:

path_segment (Iterable[PathSegmentType])

path_segment: Iterable[PathSegmentType]
id: str | None
path_segments: PathSegments | None
range: Range | None

org.accellera.ipxact.v1685_2022.sliced_access_handle module

class org.accellera.ipxact.v1685_2022.sliced_access_handle.SlicedAccessHandle(view_ref=<factory>, slices=None, vendor_extensions=None, force=True, id=None)

Bases: object

Variables:

  • view_ref – A list of views this accessHandle is applicable to. Note this element is optional, if it is not present the accessHandle applies to all views.

  • slices

  • vendor_extensions

  • force

  • id

Parameters:
class ViewRef(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
force: bool
id: str | None
slices: SlicesType | None
vendor_extensions: VendorExtensions | None
view_ref: Iterable[ViewRef]

org.accellera.ipxact.v1685_2022.slices_type module

class org.accellera.ipxact.v1685_2022.slices_type.SlicesType(slice=<factory>, id=None)

Bases: object

Each slice specifies the HDL path for part of the parent IP-XACT object.

The slices must be concatenated to calculate the entire path. If there is only one slice, it is assumed to be the path for the entire IP-XACT object.

Variables:

  • slice – The HDL path for a slice of the IP-XACT object.

  • id

Parameters:

  • slice (Iterable[SliceType])

  • id (str | None)

id: str | None
slice: Iterable[SliceType]

org.accellera.ipxact.v1685_2022.stride module

class org.accellera.ipxact.v1685_2022.stride.Stride(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[int] = None, maximum: Optional[int] = None, id: Optional[str] = None)

Bases: UnsignedPositiveLongintExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

  • id (str | None)

id: str | None
maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.string_expression module

class org.accellera.ipxact.v1685_2022.string_expression.StringExpression(value='', other_attributes=<factory>)

Bases: ComplexBaseExpression

Represents a string.

It supports an expression value.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.struct_port_type_defs module

class org.accellera.ipxact.v1685_2022.struct_port_type_defs.StructPortTypeDefs(struct_port_type_def: collections.abc.Iterable['StructPortTypeDefs.StructPortTypeDef'] = <factory>)

Bases: object

Parameters:

struct_port_type_def (Iterable[StructPortTypeDef])

class StructPortTypeDef(type_name=None, type_definition=<factory>, type_parameters=None, role=None, view_ref=<factory>, id=None)

Bases: object

Variables:

  • type_name

  • type_definition – Where the definition of the type is contained. For SystemC and SystemVerilog it is the include file containing the type definition.

  • type_parameters

  • role – Indicates the role that this structured port plays in the connection. Only valid for structured ports with structType=’interface’. In SystemVerilog, this indicates the modport for the SystemVerilog interface corresponding to this structuredPortType.

  • view_ref – A reference to a view name in the file for which this type applies.

  • id

Parameters:
class TypeDefinition(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
class TypeName(value='', constrained=<factory>)

Bases: object

Variables:

  • value

  • constrained – Defines the types for the port has constrained the number of bits in the vector

Parameters:

  • value (str)

  • constrained (Iterable[str])

constrained: Iterable[str]
value: str
class TypeParameters(type_parameter: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.type_parameter.TypeParameter] = <factory>)

Bases: object

Parameters:

type_parameter (Iterable[TypeParameter])

type_parameter: Iterable[TypeParameter]
class ViewRef(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
id: str | None
role: str | None
type_definition: Iterable[TypeDefinition]
type_name: TypeName | None
type_parameters: TypeParameters | None
view_ref: Iterable[ViewRef]
struct_port_type_def: Iterable[StructPortTypeDef]

org.accellera.ipxact.v1685_2022.sub_port_reference module

class org.accellera.ipxact.v1685_2022.sub_port_reference.SubPortReference(part_select=None, sub_port_ref=None, id=None)

Bases: object

Variables:

  • part_select

  • sub_port_ref – A subPort on the referenced structured port.

  • id

Parameters:

  • part_select (PartSelect | None)

  • sub_port_ref (str | None)

  • id (str | None)

id: str | None
part_select: PartSelect | None
sub_port_ref: str | None

org.accellera.ipxact.v1685_2022.sub_port_type module

class org.accellera.ipxact.v1685_2022.sub_port_type.PortStructuredType(struct=None, union=None, interface=None, vectors=None, sub_ports=None, struct_port_type_defs=None, packed=True)

Bases: object

Variables:

  • struct

  • union

  • interface

  • vectors – Vectored information.

  • sub_ports

  • struct_port_type_defs

  • packed – When not present or set to ‘true’ indicates that this structured port is ‘packed’. If present and set to ‘false’, indicates that this structured port is ‘unpacked’.

Parameters:
class Interface(phantom: bool | None = None)

Bases: object

Parameters:

phantom (bool | None)

phantom: bool | None
class Struct(direction=None)

Bases: object

Variables:

direction – The direction of a wire style port. The basic directions for a port are ‘in’ for input ports, ‘out’ for output port and ‘inout’ for bidirectional and tristate ports. A value of ‘phantom’ is also allowed and define a port that exist on the IP-XACT component but not on the HDL model.

Parameters:

direction (ComponentPortDirectionType | None)

direction: ComponentPortDirectionType | None
class SubPorts(sub_port: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.sub_port_type.SubPortType] = <factory>)

Bases: object

Parameters:

sub_port (Iterable[SubPortType])

sub_port: Iterable[SubPortType]
class UnionType(direction=None)

Bases: object

Variables:

direction – The direction of a wire style port. The basic directions for a port are ‘in’ for input ports, ‘out’ for output port and ‘inout’ for bidirectional and tristate ports. A value of ‘phantom’ is also allowed and define a port that exist on the IP-XACT component but not on the HDL model.

Parameters:

direction (ComponentPortDirectionType | None)

direction: ComponentPortDirectionType | None
interface: Interface | None
packed: bool
struct: Struct | None
struct_port_type_defs: StructPortTypeDefs | None
sub_ports: SubPorts | None
union: UnionType | None
vectors: ExtendedVectorsType | None
class org.accellera.ipxact.v1685_2022.sub_port_type.SubPortType(name=None, display_name=None, short_description=None, description=None, wire=None, structured=None, arrays=None, access=None, vendor_extensions=None, id=None, is_io=None)

Bases: object

A port description, giving a name and an access type for high level ports.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • wire – Defines a port whose type resolves to simple bits.

  • structured

  • arrays

  • access – Port access characteristics.

  • vendor_extensions

  • id

  • is_io – When present and set to ‘true’ identifies this port as being an I/O to the containing structure port type. Only valid for subPorts contained in a structured port with structType=’interface’.

Parameters:
access: PortAccessType1 | None
arrays: Arrays | None
description: Description | None
display_name: DisplayName | None
id: str | None
is_io: bool | None
name: str | None
short_description: ShortDescription | None
structured: PortStructuredType | None
vendor_extensions: VendorExtensions | None
wire: PortWireType | None

org.accellera.ipxact.v1685_2022.subspace_map module

class org.accellera.ipxact.v1685_2022.subspace_map.SubspaceMap(name=None, display_name=None, short_description=None, description=None, base_address=None, parameters=None, vendor_extensions=None, initiator_ref=None, segment_ref=None, id=None)

Bases: SubspaceRefType

Maps in an address subspace from across a bus bridge.

Its initiatorRef attribute refers by name to the initiator bus interface on the other side of the bridge. It must match the initiatorRef attribute of a bridge element on the target interface, and that bridge element must be designated as opaque.

Parameters:
base_address: SignedLongintExpression | None
description: Description | None
display_name: DisplayName | None
id: str | None
initiator_ref: str | None
name: str | None
parameters: Parameters | None
segment_ref: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.subspace_ref_type module

class org.accellera.ipxact.v1685_2022.subspace_ref_type.SubspaceRefType(name=None, display_name=None, short_description=None, description=None, base_address=None, parameters=None, vendor_extensions=None, initiator_ref=None, segment_ref=None, id=None)

Bases: object

Address subspace type.

Its subspaceReference attribute references the subspace from which the dimensions are taken.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • base_address – Base of a subspace map. Expressed as the number of addressable units from the containing memoryMap.

  • parameters – Any parameters that may apply to the subspace reference.

  • vendor_extensions

  • initiator_ref – For subspaceMap elements, this attribute identifies the initiator that contains the address space to be mapped.

  • segment_ref – Refernce to a segment of the addressSpace of the initiatorRef attribute.

  • id

Parameters:
base_address: SignedLongintExpression | None
description: Description | None
display_name: DisplayName | None
id: str | None
initiator_ref: str | None
name: str | None
parameters: Parameters | None
segment_ref: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.testable_test_constraint module

class org.accellera.ipxact.v1685_2022.testable_test_constraint.TestableTestConstraint(*values)

Bases: Enum

READ_ONLY = 'readOnly'
RESTORE = 'restore'
UNCONSTRAINED = 'unconstrained'
WRITE_AS_READ = 'writeAsRead'

org.accellera.ipxact.v1685_2022.timing_constraint module

class org.accellera.ipxact.v1685_2022.timing_constraint.TimingConstraint(value=None, clock_edge=None, delay_type=None, clock_name=None, id=None)

Bases: object

Defines a timing constraint for the associated port.

The constraint is relative to the clock specified by the clockName attribute. The clockEdge indicates which clock edge the constraint is associated with (default is rising edge). The delayType attribute can be specified to further refine the constraint.

Variables:

  • value

  • clock_edge – Indicates the clock edge that a timing constraint is relative to.

  • delay_type – Indicates the type of delay in a timing constraint - minimum or maximum.

  • clock_name – Indicates the name of the clock to which this constraint applies.

  • id

Parameters:
clock_edge: EdgeValueType | None
clock_name: str | None
delay_type: DelayValueType | None
id: str | None
value: float | None

org.accellera.ipxact.v1685_2022.trans_type_def module

class org.accellera.ipxact.v1685_2022.trans_type_def.TransTypeDef(type_name=None, type_definition=<factory>, type_parameters=None, view_ref=<factory>, id=None)

Bases: object

Definition of a single transactional type defintion.

Variables:

  • type_name – The name of the port type. Can be any predefined type such sc_port or sc_export in SystemC or any user-defined type such as tlm_port.

  • type_definition – Where the definition of the type is contained. For SystemC and SystemVerilog it is the include file containing the type definition.

  • type_parameters

  • view_ref – A reference to a view name in the file for which this type applies.

  • id

Parameters:
class TypeDefinition(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
class TypeName(value='', exact=True)

Bases: object

Variables:

  • value

  • exact – When false, defines that the type is an abstract type that may not be related to an existing type in the language of the referenced view.

Parameters:

  • value (str)

  • exact (bool)

exact: bool
value: str
class ViewRef(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
id: str | None
type_definition: Iterable[TypeDefinition]
type_name: TypeName | None
type_parameters: TypeParameters | None
view_ref: Iterable[ViewRef]

org.accellera.ipxact.v1685_2022.trans_type_defs module

class org.accellera.ipxact.v1685_2022.trans_type_defs.TransTypeDefs(trans_type_def=<factory>)

Bases: object

The group of transactional type definitions.

If no match to a viewName is found then the default language types are to be used. See the User Guide for these default types.

Parameters:

trans_type_def (Iterable[TransTypeDef])

trans_type_def: Iterable[TransTypeDef]

org.accellera.ipxact.v1685_2022.transactional_power_constraint_type module

class org.accellera.ipxact.v1685_2022.transactional_power_constraint_type.TransactionalPowerConstraintType(power_domain_ref: org.accellera.ipxact.v1685_2022.power_domain_ref.PowerDomainRef | None = None, vendor_extensions: org.accellera.ipxact.v1685_2022.vendor_extensions.VendorExtensions | None = None, id: str | None = None)

Bases: object

Parameters:
id: str | None
power_domain_ref: PowerDomainRef | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.transparent_bridge module

class org.accellera.ipxact.v1685_2022.transparent_bridge.TransparentBridge(vendor_extensions=None, initiator_ref=None, id=None)

Bases: object

If this element is present, it indicates that the bus interface provides a transparent bridge to another initiator bus interface on the same component.

It has a initiatorRef attribute which contains the name of the other bus interface. Any target interface can bridge to multiple initiator interfaces, and multiple target interfaces can bridge to the same initiator interface.

Variables:

  • vendor_extensions

  • initiator_ref – The name of the initiator bus interface to which this interface bridges.

  • id

Parameters:

  • vendor_extensions (VendorExtensions | None)

  • initiator_ref (str | None)

  • id (str | None)

id: str | None
initiator_ref: str | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.transport_method_type module

class org.accellera.ipxact.v1685_2022.transport_method_type.TransportMethodType(*values)

Bases: Enum

FILE = 'file'

org.accellera.ipxact.v1685_2022.type_definitions module

class org.accellera.ipxact.v1685_2022.type_definitions.TypeDefinitions(vendor=None, library=None, name=None, version=None, display_name=None, short_description=None, description=None, external_type_definitions=<factory>, modes=None, views=None, field_access_policy_definitions=None, enumeration_definitions=None, field_definitions=None, register_definitions=None, register_file_definitions=None, address_block_definitions=None, bank_definitions=None, memory_map_definitions=None, memory_remap_definitions=None, reset_types=None, choices=None, parameters=None, assertions=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • vendor – Name of the vendor who supplies this file.

  • library – Name of the logical library this element belongs to.

  • name – The name of the object.

  • version – Indicates the version of the named element.

  • display_name – Name for display purposes. Typically a few words providing a more detailed and/or user-friendly name than the vlnv.

  • short_description

  • description

  • external_type_definitions

  • modes – A list of user defined component modes.

  • views – A list of user defined views.

  • field_access_policy_definitions

  • enumeration_definitions

  • field_definitions

  • register_definitions

  • register_file_definitions

  • address_block_definitions

  • bank_definitions

  • memory_map_definitions

  • memory_remap_definitions

  • reset_types – A list of user defined resetTypes applicable to this component.

  • choices

  • parameters

  • assertions

  • vendor_extensions

  • id

Parameters:
class Modes(mode: collections.abc.Iterable['TypeDefinitions.Modes.Mode'] = <factory>)

Bases: object

Parameters:

mode (Iterable[Mode])

class Mode(name=None, display_name=None, short_description=None, description=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • vendor_extensions

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
mode: Iterable[Mode]
class ResetTypes(reset_type=<factory>)

Bases: object

Variables:

reset_type – A user defined reset policy

Parameters:

reset_type (Iterable[ResetType])

class ResetType(name=None, display_name=None, short_description=None, description=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • vendor_extensions

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
reset_type: Iterable[ResetType]
class Views(view: collections.abc.Iterable['TypeDefinitions.Views.View'] = <factory>)

Bases: object

Parameters:

view (Iterable[View])

class View(name=None, display_name=None, short_description=None, description=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • vendor_extensions

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
view: Iterable[View]
address_block_definitions: AddressBlockDefinitions | None
assertions: Assertions | None
bank_definitions: BankDefinitions | None
choices: Choices | None
description: Description | None
display_name: str | None
enumeration_definitions: EnumerationDefinitions | None
external_type_definitions: Iterable[ExternalTypeDefinitions]
field_access_policy_definitions: FieldAccessPolicyDefinitions | None
field_definitions: FieldDefinitions | None
id: str | None
library: str | None
memory_map_definitions: MemoryMapDefinitions | None
memory_remap_definitions: MemoryRemapDefinitions | None
modes: Modes | None
name: str | None
parameters: Parameters | None
register_definitions: RegisterDefinitions | None
register_file_definitions: RegisterFileDefinitions | None
reset_types: ResetTypes | None
short_description: ShortDescription | None
vendor: str | None
vendor_extensions: VendorExtensions | None
version: str | None
views: Views | None

org.accellera.ipxact.v1685_2022.type_parameter module

class org.accellera.ipxact.v1685_2022.type_parameter.TypeParameter(name=None, display_name=None, short_description=None, description=None, vectors=None, arrays=None, value=None, vendor_extensions=None, id=None, parameter_id=None, prompt=None, choice_ref=None, order=None, config_groups=<factory>, minimum=None, maximum=None, type_value=FormatType.STRING, sign=None, prefix=None, unit=None, resolve=ModuleParameterTypeResolve.IMMEDIATE, other_attributes=<factory>, data_type=None, usage_type=ModuleParameterTypeUsageType.TYPED, data_type_definition=None, constrained=<factory>)

Bases: ModuleParameterType

A typed parameter name value pair.

The optional attribute dataType defines the type of the value and the usageType attribute indicates how the parameter is to be used.

Parameters:
class Vectors(vector=<factory>)

Bases: object

Variables:

vector – Left and right ranges of the vector.

Parameters:

vector (Iterable[Vector])

class Vector(left: org.accellera.ipxact.v1685_2022.left.Left | None = None, right: org.accellera.ipxact.v1685_2022.right.Right | None = None, vector_id: str | None = None, id: str | None = None)

Bases: object

Parameters:

  • left (Left | None)

  • right (Right | None)

  • vector_id (str | None)

  • id (str | None)

id: str | None
left: Left | None
right: Right | None
vector_id: str | None
vector: Iterable[Vector]
arrays: ModuleParameterArrays | None
choice_ref: str | None
config_groups: Iterable[str]
constrained: Iterable[str]
data_type: str | None
data_type_definition: str | None
description: Description | None
display_name: DisplayName | None
id: str | None
maximum: str | None
minimum: str | None
name: str | None
order: float | None
other_attributes: Mapping[str, str]
parameter_id: str | None
prefix: ModuleParameterTypePrefix | None
prompt: str | None
resolve: ModuleParameterTypeResolve
short_description: ShortDescription | None
sign: SignType | None
type_value: FormatType
unit: ModuleParameterTypeUnit | None
usage_type: ModuleParameterTypeUsageType
value: Value | None
vectors: 'ModuleParameterType.Vectors' | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.type_parameters module

class org.accellera.ipxact.v1685_2022.type_parameters.ServiceTypeDef(type_name=None, type_definition=<factory>, type_parameters=None, id=None)

Bases: object

Definition of a single service type defintion.

Variables:

  • type_name – The name of the service type. Can be any predefined type such as booean or integer or any user-defined type such as addr_type or data_type.

  • type_definition – Where the definition of the type is contained if the type if not part of the language. For SystemC and SystemVerilog it is the include file containing the type definition.

  • type_parameters

  • id

Parameters:
class TypeDefinition(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
class TypeName(value='', implicit=False)

Bases: object

Variables:

  • value

  • implicit – Defines that the typeName supplied for this service is implicit and a netlister should not declare this service in a language specific top-level netlist

Parameters:

  • value (str)

  • implicit (bool)

implicit: bool
value: str
id: str | None
type_definition: Iterable[TypeDefinition]
type_name: TypeName | None
type_parameters: TypeParameters | None
class org.accellera.ipxact.v1685_2022.type_parameters.TypeParameters(type_parameter=<factory>, service_type_def=<factory>)

Bases: object

List of port type parameters (e.g. template or constructor parameters for a systemC port or socket)

Parameters:
service_type_def: Iterable[ServiceTypeDef]
type_parameter: Iterable[TypeParameter]

org.accellera.ipxact.v1685_2022.unresolved_string_expression module

class org.accellera.ipxact.v1685_2022.unresolved_string_expression.UnresolvedStringExpression(value='', other_attributes=<factory>)

Bases: ComplexBaseExpression

Represents a string which cannot be fully resolved.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.unresolved_unsigned_bit_expression module

class org.accellera.ipxact.v1685_2022.unresolved_unsigned_bit_expression.UnresolvedUnsignedBitExpression(value='', other_attributes=<factory>)

Bases: ComplexBaseExpression

Unsigned Bit Expression which cannot be fully resolved.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.unresolved_unsigned_positive_int_expression module

class org.accellera.ipxact.v1685_2022.unresolved_unsigned_positive_int_expression.UnresolvedUnsignedPositiveIntExpression(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: ComplexBaseExpression

An positive unsigned int which supports an expression value.

Variables:

  • minimum – For elements which can be specified using expression which are supposed to be resolved to an unsiged int value, this indicates the minimum value allowed.

  • maximum – For elements which can be specified using expression which are supposed to be resolved to a unsigned int value, this indicates the maximum value allowed.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.unsigned_bit_expression module

class org.accellera.ipxact.v1685_2022.unsigned_bit_expression.UnsignedBitExpression(value='', other_attributes=<factory>)

Bases: ComplexBaseExpression

Represents a single-bit/bool.

It supports an expression value.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.unsigned_bit_vector_expression module

class org.accellera.ipxact.v1685_2022.unsigned_bit_vector_expression.UnsignedBitVectorExpression(value='', other_attributes=<factory>)

Bases: ComplexBaseExpression

Represents a bit-string.

It supports an expression value.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.unsigned_int_expression module

class org.accellera.ipxact.v1685_2022.unsigned_int_expression.UnsignedIntExpression(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: ComplexBaseExpression

An unsigned int which supports an expression value.

Variables:

  • minimum – For elements which can be specified using expression which are supposed to be resolved to an unsiged int value, this indicates the minimum value allowed.

  • maximum – For elements which can be specified using expression which are supposed to be resolved to a unsigned int value, this indicates the maximum value allowed.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.unsigned_longint_expression module

class org.accellera.ipxact.v1685_2022.unsigned_longint_expression.UnsignedLongintExpression(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: ComplexBaseExpression

An unsigned longint which supports an expression value.

Variables:

  • minimum – For elements which can be specified using expression which are supposed to be resolved to a unsigend longint value, this indicates the minimum value allowed.

  • maximum – For elements which can be specified using expression which are supposed to be resolved to an unsigend longint value, this indicates the maximum value allowed.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.unsigned_positive_int_expression module

class org.accellera.ipxact.v1685_2022.unsigned_positive_int_expression.UnsignedPositiveIntExpression(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: ComplexBaseExpression

An positive unsigned int which supports an expression value.

Variables:

  • minimum – For elements which can be specified using expression which are supposed to be resolved to an unsiged int value, this indicates the minimum value allowed.

  • maximum – For elements which can be specified using expression which are supposed to be resolved to a unsigned int value, this indicates the maximum value allowed.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.unsigned_positive_longint_expression module

class org.accellera.ipxact.v1685_2022.unsigned_positive_longint_expression.UnsignedPositiveLongintExpression(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: ComplexBaseExpression

A positive unsigned longint which supports an expression value.

Variables:

  • minimum – For elements which can be specified using expression which are supposed to be resolved to a positive unsigned longint value, this indicates the minimum value allowed.

  • maximum – For elements which can be specified using expression which are supposed to be resolved to a positive unsigned longint value, this indicates the maximum value allowed.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str

org.accellera.ipxact.v1685_2022.usage_type module

class org.accellera.ipxact.v1685_2022.usage_type.UsageType(*values)

Bases: Enum

Describes the usage of an address block.

Variables:

  • MEMORY – Denotes an address range that can be used for read- write or read-only data storage.

  • REGISTER – Denotes an address block that is used to communicate with hardware.

  • RESERVED – Denotes an address range that must remain unoccupied.

MEMORY = 'memory'
REGISTER = 'register'
RESERVED = 'reserved'

org.accellera.ipxact.v1685_2022.value module

org.accellera.ipxact.v1685_2022.vector module

class org.accellera.ipxact.v1685_2022.vector.Vector(left=None, right=None, id=None)

Bases: object

Left and right ranges of the vector.

Parameters:

  • left (Left | None)

  • right (Right | None)

  • id (str | None)

id: str | None
left: Left | None
right: Right | None

org.accellera.ipxact.v1685_2022.vectors module

class org.accellera.ipxact.v1685_2022.vectors.Vectors(vector=<factory>)

Bases: object

Vectored information.

Parameters:

vector (Iterable[Vector])

vector: Iterable[Vector]

org.accellera.ipxact.v1685_2022.vendor_extensions module

class org.accellera.ipxact.v1685_2022.vendor_extensions.VendorExtensions(any_element=<factory>)

Bases: object

Container for vendor specific extensions.

Variables:

any_element – Accepts any element(s) the content provider wants to put here, including elements from the ipxact namespace.

Parameters:

any_element (Iterable[object])

any_element: Iterable[object]

org.accellera.ipxact.v1685_2022.view_ref module

class org.accellera.ipxact.v1685_2022.view_ref.ViewRef(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str

org.accellera.ipxact.v1685_2022.volatile module

class org.accellera.ipxact.v1685_2022.volatile.Volatile(value=None)

Bases: object

Indicates whether the data is volatile.

Parameters:

value (bool | None)

value: bool | None

org.accellera.ipxact.v1685_2022.wire module

class org.accellera.ipxact.v1685_2022.wire.Wire(qualifier=None, on_system=<factory>, on_initiator=None, on_target=None, default_value=None, requires_driver=None)

Bases: object

A port that carries logic or an array of logic values.

Variables:

  • qualifier – The type of information this port carries A wire port can carry both address and data, but may not mix this with a clock or reset

  • on_system – Defines constraints for this port when present in a system bus interface with a matching group name.

  • on_initiator – Defines constraints for this port when present in a initiator bus interface.

  • on_target – Defines constraints for this port when present in a target bus interface.

  • default_value – Indicates the default value for this wire port.

  • requires_driver

Parameters:
class OnInitiator(presence=None, width=None, direction=None, mode_constraints=None, mirrored_mode_constraints=None)

Bases: object

Variables:

  • presence

  • width – Number of bits required to represent this port. Absence of this element indicates unconstrained number of bits, i.e. the component will define the number of bits in this port. The logical numbering of the port starts at 0 to width-1.

  • direction – If this element is present, the direction of this port is restricted to the specified value. The direction is relative to the non-mirrored interface.

  • mode_constraints – Specifies default constraints for the enclosing wire type port. If the mirroredModeConstraints element is not defined, then these constraints applied to this port when it appears in a ‘mode’ bus interface or a mirrored-‘mode’ bus interface. Otherwise they only apply when the port appears in a ‘mode’ bus interface.

  • mirrored_mode_constraints – Specifies default constraints for the enclosing wire type port when it appears in a mirrored-‘mode’ bus interface.

Parameters:
class Width(value='', other_attributes=<factory>, minimum=None, maximum=None, all_bits=False)

Bases: UnsignedPositiveIntExpression

Variables:

all_bits – false: mapping is optional, any number of bits can be mapped. true: mapping is required the full width is supposed to be mapped.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

  • all_bits (bool)

all_bits: bool
maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str
direction: Direction | None
mirrored_mode_constraints: AbstractionDefPortConstraintsType | None
mode_constraints: AbstractionDefPortConstraintsType | None
presence: Presence | None
width: Width | None
class OnSystem(group=None, presence=None, width=None, direction=None, mode_constraints=None, mirrored_mode_constraints=None, id=None)

Bases: object

Variables:

  • group – Used to group system ports into different groups within a common bus.

  • presence

  • width – Number of bits required to represent this port. Absence of this element indicates unconstrained number of bits, i.e. the component will define the number of bits in this port. The logical numbering of the port starts at 0 to width-1.

  • direction – If this element is present, the direction of this port is restricted to the specified value. The direction is relative to the non-mirrored interface.

  • mode_constraints – Specifies default constraints for the enclosing wire type port. If the mirroredModeConstraints element is not defined, then these constraints applied to this port when it appears in a ‘mode’ bus interface or a mirrored-‘mode’ bus interface. Otherwise they only apply when the port appears in a ‘mode’ bus interface.

  • mirrored_mode_constraints – Specifies default constraints for the enclosing wire type port when it appears in a mirrored-‘mode’ bus interface.

  • id

Parameters:
class Width(value='', other_attributes=<factory>, minimum=None, maximum=None, all_bits=False)

Bases: UnsignedPositiveIntExpression

Variables:

all_bits – false: mapping is optional, any number of bits can be mapped. true: mapping is required the full width is supposed to be mapped.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

  • all_bits (bool)

all_bits: bool
maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str
direction: Direction | None
group: str | None
id: str | None
mirrored_mode_constraints: AbstractionDefPortConstraintsType | None
mode_constraints: AbstractionDefPortConstraintsType | None
presence: Presence | None
width: Width | None
class OnTarget(presence=None, width=None, direction=None, mode_constraints=None, mirrored_mode_constraints=None)

Bases: object

Variables:

  • presence

  • width – Number of bits required to represent this port. Absence of this element indicates unconstrained number of bits, i.e. the component will define the number of bits in this port. The logical numbering of the port starts at 0 to width-1.

  • direction – If this element is present, the direction of this port is restricted to the specified value. The direction is relative to the non-mirrored interface.

  • mode_constraints – Specifies default constraints for the enclosing wire type port. If the mirroredModeConstraints element is not defined, then these constraints applied to this port when it appears in a ‘mode’ bus interface or a mirrored-‘mode’ bus interface. Otherwise they only apply when the port appears in a ‘mode’ bus interface.

  • mirrored_mode_constraints – Specifies default constraints for the enclosing wire type port when it appears in a mirrored-‘mode’ bus interface.

Parameters:
class Width(value='', other_attributes=<factory>, minimum=None, maximum=None, all_bits=False)

Bases: UnsignedPositiveIntExpression

Variables:

all_bits – false: mapping is optional, any number of bits can be mapped. true: mapping is required the full width is supposed to be mapped.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

  • all_bits (bool)

all_bits: bool
maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str
direction: Direction | None
mirrored_mode_constraints: AbstractionDefPortConstraintsType | None
mode_constraints: AbstractionDefPortConstraintsType | None
presence: Presence | None
width: Width | None
default_value: UnsignedBitVectorExpression | None
on_initiator: OnInitiator | None
on_system: Iterable[OnSystem]
on_target: OnTarget | None
qualifier: QualifierType | None
requires_driver: RequiresDriver | None

org.accellera.ipxact.v1685_2022.wire_power_constraint_type module

class org.accellera.ipxact.v1685_2022.wire_power_constraint_type.WirePowerConstraintType(power_domain_ref: org.accellera.ipxact.v1685_2022.power_domain_ref.PowerDomainRef | None = None, range: org.accellera.ipxact.v1685_2022.range.Range | None = None, vendor_extensions: org.accellera.ipxact.v1685_2022.vendor_extensions.VendorExtensions | None = None, id: str | None = None)

Bases: object

Parameters:
id: str | None
power_domain_ref: PowerDomainRef | None
range: Range | None
vendor_extensions: VendorExtensions | None

org.accellera.ipxact.v1685_2022.wire_type_def module

class org.accellera.ipxact.v1685_2022.wire_type_def.WireTypeDef(type_name=None, type_definition=<factory>, view_ref=<factory>, id=None)

Bases: object

Definition of a single wire type defintion that can relate to multiple views.

Variables:

  • type_name – The name of the logic type. Examples could be std_logic, std_ulogic, std_logic_vector, sc_logic, …

  • type_definition – Where the definition of the type is contained. For std_logic, this is contained in IEEE.std_logic_1164.all. For sc_logic, this is contained in systemc.h. For VHDL this is the library and package as defined by the “used” statement. For SystemC and SystemVerilog it is the include file required. For verilog this is not needed.

  • view_ref – A reference to a view name in the file for which this type applies.

  • id

Parameters:
class TypeDefinition(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
class TypeName(value='', constrained=<factory>)

Bases: object

Variables:

  • value

  • constrained – Defines the types for the port has constrained the number of bits in the vector

Parameters:

  • value (str)

  • constrained (Iterable[str])

constrained: Iterable[str]
value: str
class ViewRef(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
id: str | None
type_definition: Iterable[TypeDefinition]
type_name: TypeName | None
view_ref: Iterable[ViewRef]

org.accellera.ipxact.v1685_2022.wire_type_defs module

class org.accellera.ipxact.v1685_2022.wire_type_defs.WireTypeDefs(wire_type_def=<factory>)

Bases: object

The group of wire type definitions.

If no match to a viewName is found then the default language types are to be used. See the User Guide for these default types.

Parameters:

wire_type_def (Iterable[WireTypeDef])

wire_type_def: Iterable[WireTypeDef]

org.accellera.ipxact.v1685_2022.write_value_constraint module

class org.accellera.ipxact.v1685_2022.write_value_constraint.WriteValueConstraint(write_as_read=None, use_enumerated_values=None, minimum=None, maximum=None)

Bases: WriteValueConstraintType

The legal values that may be written to a field.

If not specified the legal values are not specified.

Parameters:
maximum: UnsignedBitVectorExpression | None
minimum: UnsignedBitVectorExpression | None
use_enumerated_values: bool | None
write_as_read: bool | None

org.accellera.ipxact.v1685_2022.write_value_constraint_type module

class org.accellera.ipxact.v1685_2022.write_value_constraint_type.WriteValueConstraintType(write_as_read=None, use_enumerated_values=None, minimum=None, maximum=None)

Bases: object

A constraint on the values that can be written to this field.

Absence of this element implies that any value that fits can be written to it.

Variables:

  • write_as_read – writeAsRead indicates that only a value immediately read before a write is a legal value to be written.

  • use_enumerated_values – useEnumeratedValues indicates that only write enumeration value shall be legal values to be written.

  • minimum – The minimum legal value that may be written to a field

  • maximum – The maximum legal value that may be written to a field

Parameters:
maximum: UnsignedBitVectorExpression | None
minimum: UnsignedBitVectorExpression | None
use_enumerated_values: bool | None
write_as_read: bool | None

Module contents

class org.accellera.ipxact.v1685_2022.AbstractionDefPortConstraintsType(timing_constraint=<factory>, drive_constraint=<factory>, load_constraint=<factory>)

Bases: object

Defines constraints that apply to a wire type port in an abstraction definition.

Parameters:
drive_constraint: Iterable[DriveConstraint]
load_constraint: Iterable[LoadConstraint]
timing_constraint: Iterable[TimingConstraint]
class org.accellera.ipxact.v1685_2022.AbstractionDefinition(vendor=None, library=None, name=None, version=None, display_name=None, short_description=None, description=None, bus_type=None, extends=None, ports=None, choices=None, parameters=None, assertions=None, vendor_extensions=None, id=None)

Bases: object

Define the ports and other information of a particular abstraction of the bus.

Variables:

  • vendor – Name of the vendor who supplies this file.

  • library – Name of the logical library this element belongs to.

  • name – The name of the object.

  • version – Indicates the version of the named element.

  • display_name – Name for display purposes. Typically a few words providing a more detailed and/or user-friendly name than the vlnv.

  • short_description

  • description

  • bus_type – Reference to the busDefinition that this abstractionDefinition implements.

  • extends – Optional name of abstraction type that this abstraction definition is compatible with. This abstraction definition may change the definitions of ports in the existing abstraction definition and add new ports, the ports in the original abstraction are not deleted but may be marked illegal to disallow their use. This abstraction definition may only extend another abstraction definition if the bus type of this abstraction definition extends the bus type of the extended abstraction definition

  • ports – This is a list of logical ports defined by the bus.

  • choices

  • parameters

  • assertions

  • vendor_extensions

  • id

Parameters:
class Ports(port: collections.abc.Iterable['AbstractionDefinition.Ports.Port'] = <factory>)

Bases: object

Parameters:

port (Iterable[Port])

class Port(logical_name=None, display_name=None, short_description=None, description=None, match=None, wire=None, transactional=None, packets=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • logical_name – The assigned name of this port in bus specifications.

  • display_name

  • short_description

  • description

  • match – If this element is enabled (true) it is an error if the port is not mapped on both sides of the connection.

  • wire

  • transactional – A port that carries complex information modeled at a high level of abstraction.

  • packets

  • vendor_extensions

  • id

Parameters:
class Transactional(qualifier=None, on_system=<factory>, on_initiator=None, on_target=None)

Bases: object

Variables:

  • qualifier – The type of information this port carries A transactional port can carry both address and data information.

  • on_system – Defines constraints for this port when present in a system bus interface with a matching group name.

  • on_initiator – Defines constraints for this port when present in a initiator bus interface.

  • on_target – Defines constraints for this port when present in a target bus interface.

Parameters:
class OnInitiator(presence=None, initiative=None, kind=None, bus_width=None, protocol=None)

Bases: object

Variables:

  • presence

  • initiative – If this element is present, the type of access is restricted to the specified value.

  • kind

  • bus_width – If this element is present, the width must match

  • protocol – If this element is present, the name must match

Parameters:
bus_width: UnsignedPositiveIntExpression | None
initiative: OnInitiatorInitiative | None
kind: Kind | None
presence: Presence | None
protocol: Protocol | None
class OnSystem(group=None, presence=None, initiative=None, kind=None, bus_width=None, protocol=None, id=None)

Bases: object

Variables:

  • group – Used to group system ports into different groups within a common bus.

  • presence

  • initiative – If this element is present, the type of access is restricted to the specified value.

  • kind

  • bus_width – If this element is present, the width must match

  • protocol – If this element is present, the name must match

  • id

Parameters:
bus_width: UnsignedPositiveIntExpression | None
group: str | None
id: str | None
initiative: OnSystemInitiative | None
kind: Kind | None
presence: Presence | None
protocol: Protocol | None
class OnTarget(presence=None, initiative=None, kind=None, bus_width=None, protocol=None)

Bases: object

Variables:

  • presence

  • initiative – If this element is present, the type of access is restricted to the specified value.

  • kind

  • bus_width – If this element is present, the width must match

  • protocol – If this element is present, the name must match

Parameters:
bus_width: UnsignedPositiveIntExpression | None
initiative: OnTargetInitiative | None
kind: Kind | None
presence: Presence | None
protocol: Protocol | None
on_initiator: OnInitiator | None
on_system: Iterable[OnSystem]
on_target: OnTarget | None
qualifier: QualifierType | None
description: Description | None
display_name: DisplayName | None
id: str | None
logical_name: str | None
match: bool | None
packets: Packets | None
short_description: ShortDescription | None
transactional: Transactional | None
vendor_extensions: VendorExtensions | None
wire: Wire | None
port: Iterable[Port]
assertions: Assertions | None
bus_type: LibraryRefType | None
choices: Choices | None
description: Description | None
display_name: str | None
extends: LibraryRefType | None
id: str | None
library: str | None
name: str | None
parameters: Parameters | None
ports: Ports | None
short_description: ShortDescription | None
vendor: str | None
vendor_extensions: VendorExtensions | None
version: str | None
class org.accellera.ipxact.v1685_2022.AbstractionTypes(abstraction_type=<factory>)

Bases: object

Variables:

abstraction_type – The abstraction type/level of this interface. Refers to abstraction definition using vendor, library, name, version attributes along with any configurable element values needed to configure this abstraction. Bus definition can be found through a reference in this file.

Parameters:

abstraction_type (Iterable[AbstractionType])

class AbstractionType(view_ref=<factory>, abstraction_ref=None, port_maps=None, id=None)

Bases: object

Variables:

  • view_ref – A reference to a view name in the file for which this type applies.

  • abstraction_ref – Provides the VLNV of the abstraction type.

  • port_maps – Listing of maps between component ports and bus ports.

  • id

Parameters:
class PortMaps(port_map=<factory>)

Bases: object

Variables:

port_map – Maps a component’s port to a port in a bus description. This is the logical to physical mapping. The logical pin comes from the bus interface and the physical pin from the component.

Parameters:

port_map (Iterable[PortMap])

class PortMap(logical_port=None, physical_port=None, logical_tie_off=None, is_informative=None, vendor_extensions=None, id=None, invert='false')

Bases: object

Variables:

  • logical_port – Logical port from abstraction definition

  • physical_port – Physical port from this component

  • logical_tie_off – Identifies a value to tie this logical port to.

  • is_informative – When true, indicates that this portMap element is for information purpose only.

  • vendor_extensions

  • id

  • invert – Indicates that the connection between the logical and physical ports should include an inversion.

Parameters:
class LogicalPort(name=None, range=None, id=None)

Bases: object

Variables:

  • name – Bus port name as specified inside the abstraction definition

  • range

  • id

Parameters:

  • name (str | None)

  • range (Range | None)

  • id (str | None)

id: str | None
name: str | None
range: Range | None
class PhysicalPort(name=None, part_select=None, sub_port=<factory>, id=None)

Bases: object

Variables:

  • name – Component port name as specified inside the model port section

  • part_select

  • sub_port

  • id

Parameters:

  • name (str | None)

  • part_select (PartSelect | None)

  • sub_port (Iterable[SubPort])

  • id (str | None)

class SubPort(name=None, part_select=None, id=None)

Bases: object

Variables:

  • name – Component port subPort name as specified inside the model port section

  • part_select

  • id

Parameters:

  • name (str | None)

  • part_select (PartSelect | None)

  • id (str | None)

id: str | None
name: str | None
part_select: PartSelect | None
id: str | None
name: str | None
part_select: PartSelect | None
sub_port: Iterable[SubPort]
id: str | None
invert: object
is_informative: bool | None
logical_port: LogicalPort | None
logical_tie_off: UnsignedBitVectorExpression | None
physical_port: PhysicalPort | None
vendor_extensions: VendorExtensions | None
port_map: Iterable[PortMap]
abstraction_ref: ConfigurableLibraryRefType | None
id: str | None
port_maps: PortMaps | None
view_ref: Iterable[ViewRef]
abstraction_type: Iterable[AbstractionType]
class org.accellera.ipxact.v1685_2022.Abstractor(vendor=None, library=None, name=None, version=None, display_name=None, short_description=None, description=None, abstractor_mode=None, bus_type=None, abstractor_interfaces=None, model=None, abstractor_generators=None, choices=None, file_sets=None, parameters=None, assertions=None, vendor_extensions=None, id=None)

Bases: AbstractorType

This is the root element for abstractors.

Parameters:
class AbstractorInterfaces(abstractor_interface=<factory>)

Bases: object

Variables:

abstractor_interface – An abstractor must have exactly 2 Interfaces.

Parameters:

abstractor_interface (Iterable[AbstractorBusInterfaceType])

abstractor_interface: Iterable[AbstractorBusInterfaceType]
class AbstractorMode(value=None, group=None)

Bases: object

Variables:

  • value

  • group – Define the system group if the mode is set to system

Parameters:
group: str | None
value: AbstractorModeType | None
abstractor_generators: AbstractorGenerators | None
abstractor_interfaces: 'AbstractorType.AbstractorInterfaces' | None
abstractor_mode: 'AbstractorType.AbstractorMode' | None
assertions: Assertions | None
bus_type: LibraryRefType | None
choices: Choices | None
description: Description | None
display_name: str | None
file_sets: FileSets | None
id: str | None
library: str | None
model: AbstractorModelType | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
vendor: str | None
vendor_extensions: VendorExtensions | None
version: str | None
class org.accellera.ipxact.v1685_2022.AbstractorBusInterfaceType(name=None, display_name=None, short_description=None, description=None, abstraction_types=None, parameters=None, vendor_extensions=None, id=None, other_attributes=<factory>)

Bases: object

Type definition for a busInterface in a component.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • abstraction_types

  • parameters

  • vendor_extensions

  • id

  • other_attributes

Parameters:
abstraction_types: AbstractionTypes | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
other_attributes: Mapping[str, str]
parameters: Parameters | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.AbstractorGenerator(name=None, display_name=None, short_description=None, description=None, phase=None, parameters=None, api_type=None, api_service=None, transport_methods=None, generator_exe=None, vendor_extensions=None, hidden=False, id=None, group=<factory>, scope=InstanceGeneratorTypeScope.INSTANCE)

Bases: InstanceGeneratorType

Specifies a set of abstractor generators.

The scope attribute applies to abstractor generators and specifies whether the generator should be run for each instance of the entity (or module) or just once for all instances of the entity.

Parameters:
api_service: GeneratorTypeApiService | None
api_type: 'GeneratorType.ApiType' | None
description: Description | None
display_name: DisplayName | None
generator_exe: IpxactUri | None
group: Iterable['InstanceGeneratorType.Group']
hidden: bool
id: str | None
name: str | None
parameters: Parameters | None
phase: Phase | None
scope: InstanceGeneratorTypeScope
short_description: ShortDescription | None
transport_methods: 'GeneratorType.TransportMethods' | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.AbstractorGenerators(abstractor_generator=<factory>)

Bases: object

List of abstractor generators.

Parameters:

abstractor_generator (Iterable[AbstractorGenerator])

abstractor_generator: Iterable[AbstractorGenerator]
class org.accellera.ipxact.v1685_2022.AbstractorModeType(*values)

Bases: Enum

Mode for this abstractor.

DIRECT = 'direct'
INITIATOR = 'initiator'
SYSTEM = 'system'
TARGET = 'target'
class org.accellera.ipxact.v1685_2022.AbstractorModelType(views=None, instantiations=None, ports=None)

Bases: object

Model information for an abstractor.

Variables:

  • views – Views container

  • instantiations – Instantiations container

  • ports – Port container

Parameters:
class Instantiations(component_instantiation=<factory>)

Bases: object

Variables:

component_instantiation – Component Instantiation

Parameters:

component_instantiation (Iterable[ComponentInstantiationType])

component_instantiation: Iterable[ComponentInstantiationType]
class Ports(port: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.abstractor_port_type.AbstractorPortType] = <factory>)

Bases: object

Parameters:

port (Iterable[AbstractorPortType])

port: Iterable[AbstractorPortType]
class Views(view=<factory>)

Bases: object

Variables:

view – Single view of an abstracto

Parameters:

view (Iterable[View])

class View(name=None, display_name=None, short_description=None, description=None, env_identifier=<factory>, component_instantiation_ref=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • env_identifier – Defines the hardware environment in which this view applies. The format of the string is language:tool:vendor_extension, with each piece being optional. The language must be one of the types from ipxact:fileType. The tool values are defined by the Accellera Systems Initiative, and include generic values “*Simulation” and “*Synthesis” to imply any tool of the indicated type. Having more than one envIdentifier indicates that the view applies to multiple environments.

  • component_instantiation_ref

  • vendor_extensions

  • id

Parameters:
class EnvIdentifier(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
component_instantiation_ref: str | None
description: Description | None
display_name: DisplayName | None
env_identifier: Iterable[EnvIdentifier]
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
view: Iterable[View]
instantiations: Instantiations | None
ports: Ports | None
views: Views | None
class org.accellera.ipxact.v1685_2022.AbstractorPortStructuredType(struct=None, union=None, interface=None, vectors=None, sub_ports=None, struct_port_type_defs=None, packed=True)

Bases: object

Variables:

  • struct

  • union

  • interface

  • vectors – Vectored information.

  • sub_ports

  • struct_port_type_defs

  • packed – When not present or set to ‘true’ indicates that this structured port is ‘packed’. If present and set to ‘false’, indicates that this structured port is ‘unpacked’.

Parameters:
class Interface(phantom: bool | None = None)

Bases: object

Parameters:

phantom (bool | None)

phantom: bool | None
class Struct(direction=None)

Bases: object

Variables:

direction – The direction of a wire style port. The basic directions for a port are ‘in’ for input ports, ‘out’ for output port and ‘inout’ for bidirectional and tristate ports. A value of ‘phantom’ is also allowed and define a port that exist on the IP-XACT component but not on the HDL model.

Parameters:

direction (ComponentPortDirectionType | None)

direction: ComponentPortDirectionType | None
class SubPorts(sub_port: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.abstractor_sub_port_type.AbstractorSubPortType] = <factory>)

Bases: object

Parameters:

sub_port (Iterable[AbstractorSubPortType])

sub_port: Iterable[AbstractorSubPortType]
class UnionType(direction=None)

Bases: object

Variables:

direction – The direction of a wire style port. The basic directions for a port are ‘in’ for input ports, ‘out’ for output port and ‘inout’ for bidirectional and tristate ports. A value of ‘phantom’ is also allowed and define a port that exist on the IP-XACT component but not on the HDL model.

Parameters:

direction (ComponentPortDirectionType | None)

direction: ComponentPortDirectionType | None
interface: Interface | None
packed: bool
struct: Struct | None
struct_port_type_defs: StructPortTypeDefs | None
sub_ports: SubPorts | None
union: UnionType | None
vectors: ExtendedVectorsType | None
class org.accellera.ipxact.v1685_2022.AbstractorPortTransactionalType(initiative=None, kind=None, bus_width=None, qualifier=None, protocol=None, trans_type_defs=None, connection=None, all_logical_initiatives_allowed=False)

Bases: object

Transactional port type.

Variables:

  • initiative – Defines how the port accesses this service.

  • kind – Define the kind of transactional port

  • bus_width – Defines the bus width in bits.This can be the result of an expression.

  • qualifier – The type of information this port carries A transactional port can carry both address and data information.

  • protocol – Defines the protocol type. Defaults to tlm_base_protocol_type for TLM sockets

  • trans_type_defs – Definition of the port type expressed in the default language for this port (i.e. SystemC or SystemV).

  • connection – Bounds number of legal connections.

  • all_logical_initiatives_allowed – True if logical ports with different initiatives from the physical port initiative may be mapped onto this port. Forbidden for phantom ports, which always allow logical ports with all initiatives value to be mapped onto the physical port. Also ignored for “both” ports, since any logical port may be mapped to a physical “both” port.

Parameters:
class Connection(max_connections=None, min_connections=None)

Bases: object

Variables:

  • max_connections – Indicates the maximum number of connections this port supports. If this element is not present or set to 0 it implies an unbounded number of allowed connections.

  • min_connections – Indicates the minimum number of connections this port supports. If this element is not present, the minimum number of allowed connections is 1.

Parameters:
max_connections: UnsignedIntExpression | None
min_connections: UnsignedIntExpression | None
all_logical_initiatives_allowed: bool
bus_width: BusWidth | None
connection: Connection | None
initiative: Initiative | None
kind: Kind | None
protocol: Protocol | None
qualifier: QualifierType | None
trans_type_defs: TransTypeDefs | None
class org.accellera.ipxact.v1685_2022.AbstractorPortType(name=None, display_name=None, short_description=None, description=None, wire=None, transactional=None, structured=None, arrays=None, access=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

A port description, giving a name and an access type for high level ports.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • wire – Defines a port whose type resolves to simple bits.

  • transactional – Defines a port that implements or uses a service that can be implemented with functions or methods.

  • structured – Represents a port that has subport structure.

  • arrays

  • access – Port access characteristics.

  • parameters

  • vendor_extensions

  • id

Parameters:
access: PortAccessType1 | None
arrays: Arrays | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
structured: AbstractorPortStructuredType | None
transactional: AbstractorPortTransactionalType | None
vendor_extensions: VendorExtensions | None
wire: AbstractorPortWireType | None
class org.accellera.ipxact.v1685_2022.AbstractorPortWireType(direction=None, qualifier=None, vectors=None, wire_type_defs=None, domain_type_defs=None, signal_type_defs=None, drivers=None, all_logical_directions_allowed=False)

Bases: PortWireType

Wire port type for an abstractor.

Variables:

  • constraint_sets

  • power_constraints – Wire port power constraints.

Parameters:
class PowerConstraints(power_constraint=<factory>)

Bases: object

Variables:

power_constraint – Single wire port set of power constraints.

Parameters:

power_constraint (Iterable[WirePowerConstraintType])

power_constraint: Iterable[WirePowerConstraintType]
all_logical_directions_allowed: bool
constraint_sets: Any
direction: ComponentPortDirectionType | None
domain_type_defs: DomainTypeDefs | None
drivers: Drivers | None
power_constraints: Any
qualifier: QualifierType | None
signal_type_defs: SignalTypeDefs | None
vectors: ExtendedVectorsType | None
wire_type_defs: WireTypeDefs | None
class org.accellera.ipxact.v1685_2022.AbstractorSubPortType(name=None, display_name=None, short_description=None, description=None, wire=None, structured=None, arrays=None, access=None, vendor_extensions=None, id=None, is_io=None)

Bases: object

A port description, giving a name and an access type for high level ports.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • wire – Defines a port whose type resolves to simple bits.

  • structured

  • arrays

  • access – Port access characteristics.

  • vendor_extensions

  • id

  • is_io – When present and set to ‘true’ identifies this port as being an I/O to the containing structure port type. Only valid for subPorts contained in a structured port with structType=’interface’.

Parameters:
access: PortAccessType1 | None
arrays: Arrays | None
description: Description | None
display_name: DisplayName | None
id: str | None
is_io: bool | None
name: str | None
short_description: ShortDescription | None
structured: AbstractorPortStructuredType | None
vendor_extensions: VendorExtensions | None
wire: AbstractorPortWireType | None
class org.accellera.ipxact.v1685_2022.AbstractorType(vendor=None, library=None, name=None, version=None, display_name=None, short_description=None, description=None, abstractor_mode=None, bus_type=None, abstractor_interfaces=None, model=None, abstractor_generators=None, choices=None, file_sets=None, parameters=None, assertions=None, vendor_extensions=None, id=None)

Bases: object

Abstractor-specific extension to abstractorType.

Variables:

  • vendor – Name of the vendor who supplies this file.

  • library – Name of the logical library this element belongs to.

  • name – The name of the object.

  • version – Indicates the version of the named element.

  • display_name – Name for display purposes. Typically a few words providing a more detailed and/or user-friendly name than the vlnv.

  • short_description

  • description

  • abstractor_mode – Define the mode for the interfaces on this abstractor. For initiator the first interface connects to the initiator, the second connects to the mirroredInitiator For target the first interface connects to the mirroredTarget the second connects to the target For direct the first interface connects to the initiator, the second connects to the target For system the first interface connects to the system, the second connects to the mirroredSystem. For system the group attribute is required

  • bus_type – The bus type of both interfaces. Refers to bus definition using vendor, library, name, version attributes.

  • abstractor_interfaces – The interfaces supported by this abstractor

  • model – Model information.

  • abstractor_generators – Generator list is tools-specific.

  • choices

  • file_sets

  • parameters

  • assertions

  • vendor_extensions

  • id

Parameters:
class AbstractorInterfaces(abstractor_interface=<factory>)

Bases: object

Variables:

abstractor_interface – An abstractor must have exactly 2 Interfaces.

Parameters:

abstractor_interface (Iterable[AbstractorBusInterfaceType])

abstractor_interface: Iterable[AbstractorBusInterfaceType]
class AbstractorMode(value=None, group=None)

Bases: object

Variables:

  • value

  • group – Define the system group if the mode is set to system

Parameters:
group: str | None
value: AbstractorModeType | None
abstractor_generators: AbstractorGenerators | None
abstractor_interfaces: AbstractorInterfaces | None
abstractor_mode: AbstractorMode | None
assertions: Assertions | None
bus_type: LibraryRefType | None
choices: Choices | None
description: Description | None
display_name: str | None
file_sets: FileSets | None
id: str | None
library: str | None
model: AbstractorModelType | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
vendor: str | None
vendor_extensions: VendorExtensions | None
version: str | None
class org.accellera.ipxact.v1685_2022.Access(value: org.accellera.ipxact.v1685_2022.access_type.AccessType | None = None)

Bases: object

Parameters:

value (AccessType | None)

value: AccessType | None
class org.accellera.ipxact.v1685_2022.AccessPolicies(access_policy: collections.abc.Iterable['AccessPolicies.AccessPolicy'] = <factory>)

Bases: object

Parameters:

access_policy (Iterable[AccessPolicy])

class AccessPolicy(mode_ref: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.mode_ref.ModeRef] = <factory>, access: Optional[org.accellera.ipxact.v1685_2022.access_type.AccessType] = None, vendor_extensions: Optional[org.accellera.ipxact.v1685_2022.vendor_extensions.VendorExtensions] = None, id: Optional[str] = None)

Bases: object

Parameters:

  • mode_ref (Iterable[ModeRef])

  • access (AccessType | None)

  • vendor_extensions (VendorExtensions | None)

  • id (str | None)

access: AccessType | None
id: str | None
mode_ref: Iterable[ModeRef]
vendor_extensions: VendorExtensions | None
access_policy: Iterable[AccessPolicy]
class org.accellera.ipxact.v1685_2022.AccessPropertiesType(access_entry_type_ref=None, id=None)

Bases: object

Variables:

  • access_entry_type_ref – Reference to a user defined accessEntryType. Assumed to be DEFAULT if not present.

  • id

Parameters:

  • access_entry_type_ref (str | None)

  • id (str | None)

access_entry_type_ref: str | None
id: str | None
class org.accellera.ipxact.v1685_2022.AccessRestrictionType(mode_ref=<factory>, read_access_mask=None, write_access_mask=None, id=None)

Bases: object

Variables:

  • mode_ref

  • read_access_mask – Mask to be anded with the readable bits in this field to determine the readabe bits in this access mode. If not present, the value defaults to “all ones” meaning that read access is not blocked.

  • write_access_mask – Mask to be anded with the writable bits in this field to determine the writeable bits in this access mode. If not present, the value defaults to “all ones” meaning that write access is not blocked.

  • id

Parameters:
id: str | None
mode_ref: Iterable[ModeRef]
read_access_mask: UnsignedBitVectorExpression | None
write_access_mask: UnsignedBitVectorExpression | None
class org.accellera.ipxact.v1685_2022.AccessRestrictions(access_restriction=<factory>)

Bases: AccessRestrictionsType

Access modes.

Parameters:

access_restriction (Iterable[AccessRestrictionType])

access_restriction: Iterable[AccessRestrictionType]
class org.accellera.ipxact.v1685_2022.AccessRestrictionsType(access_restriction=<factory>)

Bases: object

Variables:

access_restriction – Access mode.

Parameters:

access_restriction (Iterable[AccessRestrictionType])

access_restriction: Iterable[AccessRestrictionType]
class org.accellera.ipxact.v1685_2022.ActiveInterface(component_instance_ref=None, bus_ref=None, id=None, description=None, exclude_ports=None, vendor_extensions=None)

Bases: InterfaceType

Variables:

  • description

  • exclude_ports – The list of physical ports to be excluded from an interface based connection. Analogous to the removing the port map element for the named ports.

  • vendor_extensions

Parameters:
class ExcludePorts(exclude_port=<factory>)

Bases: object

Variables:

exclude_port – The name of a physical port to be excluded from the interface based connection.

Parameters:

exclude_port (Iterable[ExcludePort])

class ExcludePort(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
exclude_port: Iterable[ExcludePort]
bus_ref: str | None
component_instance_ref: str | None
description: Description | None
exclude_ports: ExcludePorts | None
id: str | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.AdHocConnection(name=None, display_name=None, short_description=None, description=None, tied_value=None, port_references=None, vendor_extensions=None, id=None)

Bases: object

Represents an ad-hoc connection between component ports.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • tied_value – The logic value of this connection. The value can be an unsigned bit vector expression or the string values ‘open’ or ‘default’. Only valid for ports of style wire.

  • port_references – Liist of internal and external port references involved in the adhocConnection

  • vendor_extensions

  • id

Parameters:
class PortReferences(internal_port_reference=<factory>, external_port_reference=<factory>)

Bases: object

Variables:

  • internal_port_reference – Defines a reference to a port on a component contained within the design.

  • external_port_reference

Parameters:
class InternalPortReference(sub_port_reference=<factory>, part_select=None, vendor_extensions=None, port_ref=None, component_instance_ref=None, id=None)

Bases: object

Variables:

  • sub_port_reference

  • part_select

  • vendor_extensions

  • port_ref – A port on the on the referenced component from componentInterfaceRef.

  • component_instance_ref – A reference to the instanceName element of a component in this design.

  • id

Parameters:
component_instance_ref: str | None
id: str | None
part_select: PartSelect | None
port_ref: str | None
sub_port_reference: Iterable[SubPortReference]
vendor_extensions: VendorExtensions | None
external_port_reference: Iterable[ExternalPortReference]
internal_port_reference: Iterable[InternalPortReference]
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
port_references: PortReferences | None
short_description: ShortDescription | None
tied_value: ComplexTiedValueExpression | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.AdHocConnections(ad_hoc_connection=<factory>)

Bases: object

Defines the set of ad-hoc connections in a design.

An ad-hoc connection represents a connection between two component pins which were not connected as a result of interface connections (i.e.the pin to pin connection was made explicitly and is represented explicitly).

Parameters:

ad_hoc_connection (Iterable[AdHocConnection])

ad_hoc_connection: Iterable[AdHocConnection]
class org.accellera.ipxact.v1685_2022.AddrSpaceRefType(vendor_extensions=None, address_space_ref=None, id=None)

Bases: object

Base type for an element which references an address space.

Reference is kept in an attribute rather than the text value, so that the type may be extended with child elements if necessary.

Variables:

  • vendor_extensions

  • address_space_ref – A reference to a unique address space.

  • id

Parameters:

  • vendor_extensions (VendorExtensions | None)

  • address_space_ref (str | None)

  • id (str | None)

address_space_ref: str | None
id: str | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.AddressBankDefinitionType(name=None, display_name=None, short_description=None, description=None, access_handles=None, base_address=None, bank_definition_ref=None, address_block=<factory>, bank=<factory>, usage=None, volatile=None, access_policies=None, parameters=None, vendor_extensions=None, bank_alignment=None, id=None)

Bases: object

Top level bank the specify an address.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • base_address

  • bank_definition_ref

  • address_block – An address block within the bank. No address information is supplied.

  • bank – A nested bank of blocks within a bank. No address information is supplied.

  • usage – Indicates the usage of this block. Possible values are ‘memory’, ‘register’ and ‘reserved’.

  • volatile

  • access_policies

  • parameters – Any additional parameters needed to describe this address block to the generators.

  • vendor_extensions

  • bank_alignment – Describes whether this bank’s blocks are aligned in ‘parallel’ or ‘serial’.

  • id

Parameters:
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_block: Iterable[BankedBlockType]
bank: Iterable[Bank]
bank_alignment: BankAlignmentType | None
bank_definition_ref: BankDefinitionRef | None
base_address: BaseAddress | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
usage: UsageType | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
class org.accellera.ipxact.v1685_2022.AddressBankType(name=None, display_name=None, short_description=None, description=None, access_handles=None, base_address=None, bank_definition_ref=None, address_block=<factory>, bank=<factory>, subspace_map=<factory>, usage=None, volatile=None, access_policies=None, parameters=None, vendor_extensions=None, bank_alignment=None, id=None)

Bases: object

Top level bank the specify an address.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • base_address

  • bank_definition_ref

  • address_block – An address block within the bank. No address information is supplied.

  • bank – A nested bank of blocks within a bank. No address information is supplied.

  • subspace_map – A subspace map within the bank. No address information is supplied.

  • usage – Indicates the usage of this block. Possible values are ‘memory’, ‘register’ and ‘reserved’.

  • volatile

  • access_policies

  • parameters – Any additional parameters needed to describe this address block to the generators.

  • vendor_extensions

  • bank_alignment – Describes whether this bank’s blocks are aligned in ‘parallel’ or ‘serial’.

  • id

Parameters:
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_block: Iterable[BankedBlockType]
bank: Iterable[Bank]
bank_alignment: BankAlignmentType | None
bank_definition_ref: BankDefinitionRef | None
base_address: BaseAddress | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
subspace_map: Iterable[BankedSubspaceType]
usage: UsageType | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
class org.accellera.ipxact.v1685_2022.AddressBlock(name=None, display_name=None, short_description=None, description=None, access_handles=None, array=None, base_address=None, address_block_definition_ref=None, type_identifier=None, range=None, width=None, usage=None, volatile=None, access_policies=None, parameters=None, register=<factory>, register_file=<factory>, vendor_extensions=None, id=None, misalignment_allowed=True)

Bases: AddressBlockType

This is a single contiguous block of memory inside a memory map.

Parameters:
class AddressBlockDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
class Register(name=None, display_name=None, short_description=None, description=None, access_handles=None, array=None, address_offset=None, register_definition_ref=None, type_identifier=None, size=None, volatile=None, access_policies=None, field_value=<factory>, alternate_registers=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • array

  • address_offset – Offset from the address block’s baseAddress or the containing register file’s addressOffset, expressed as the number of addressUnitBits from the containing memoryMap or localMemoryMap.

  • register_definition_ref

  • type_identifier – Identifier name used to indicate that multiple register elements contain the exact same information for the elements in the registerDefinitionGroup.

  • size – Width of the register in bits.

  • volatile

  • access_policies

  • field_value – Describes individual bit fields within the register.

  • alternate_registers

  • parameters

  • vendor_extensions

  • id

Parameters:
class RegisterDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_offset: UnsignedLongintExpression | None
alternate_registers: AlternateRegisters | None
array: Array | None
description: Description | None
display_name: DisplayName | None
field_value: Iterable[FieldType]
id: str | None
name: str | None
parameters: Parameters | None
register_definition_ref: RegisterDefinitionRef | None
short_description: ShortDescription | None
size: UnsignedPositiveIntExpression | None
type_identifier: str | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
access_handles: 'AddressBlockType.AccessHandles' | None
access_policies: AccessPolicies | None
address_block_definition_ref: 'AddressBlockType.AddressBlockDefinitionRef' | None
array: Array | None
base_address: BaseAddress | None
description: Description | None
display_name: DisplayName | None
id: str | None
misalignment_allowed: bool
name: str | None
parameters: Parameters | None
range: UnsignedPositiveLongintExpression | None
register: Iterable['AddressBlockType.Register']
register_file: Iterable[RegisterFile]
short_description: ShortDescription | None
type_identifier: str | None
usage: UsageType | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
width: UnsignedPositiveIntExpression | None
class org.accellera.ipxact.v1685_2022.AddressBlockDefinitions(address_block_definition: collections.abc.Iterable['AddressBlockDefinitions.AddressBlockDefinition'] = <factory>)

Bases: object

Parameters:

address_block_definition (Iterable[AddressBlockDefinition])

class AddressBlockDefinition(name=None, display_name=None, short_description=None, description=None, type_identifier=None, range=None, width=None, usage=None, volatile=None, access_policies=None, parameters=None, register=<factory>, register_file=<factory>, address_unit_bits=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • type_identifier – Identifier name used to indicate that multiple addressBlock elements contain the exact same information except for the elements in the addressBlockInstanceGroup.

  • range – The address range of an address block. Expressed as the number of addressable units accessible to the block. The range and the width are related by the following formulas: number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range number_of_rows_in_block = number_of_bits_in_block / ipxact:width

  • width – The bit width of a row in the address block. The range and the width are related by the following formulas: number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range number_of_rows_in_block = number_of_bits_in_block / ipxact:width

  • usage – Indicates the usage of this block. Possible values are ‘memory’, ‘register’ and ‘reserved’.

  • volatile

  • access_policies

  • parameters – Any additional parameters needed to describe this address block to the generators.

  • register – A single register

  • register_file – A structure of registers and register files

  • address_unit_bits

  • vendor_extensions

  • id

Parameters:
class Register(name=None, display_name=None, short_description=None, description=None, access_handles=None, array=None, address_offset=None, register_definition_ref=None, type_identifier=None, size=None, volatile=None, access_policies=None, field_value=<factory>, alternate_registers=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • array

  • address_offset – Offset from the address block’s baseAddress or the containing register file’s addressOffset, expressed as the number of addressUnitBits from the containing memoryMap or localMemoryMap.

  • register_definition_ref

  • type_identifier – Identifier name used to indicate that multiple register elements contain the exact same information for the elements in the registerDefinitionGroup.

  • size – Width of the register in bits.

  • volatile

  • access_policies

  • field_value – Describes individual bit fields within the register.

  • alternate_registers

  • parameters

  • vendor_extensions

  • id

Parameters:
class RegisterDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_offset: UnsignedLongintExpression | None
alternate_registers: AlternateRegisters | None
array: Array | None
description: Description | None
display_name: DisplayName | None
field_value: Iterable[FieldType]
id: str | None
name: str | None
parameters: Parameters | None
register_definition_ref: RegisterDefinitionRef | None
short_description: ShortDescription | None
size: UnsignedPositiveIntExpression | None
type_identifier: str | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
access_policies: AccessPolicies | None
address_unit_bits: AddressUnitBits | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
range: UnsignedPositiveLongintExpression | None
register: Iterable[Register]
register_file: Iterable[RegisterFile]
short_description: ShortDescription | None
type_identifier: str | None
usage: UsageType | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
width: UnsignedPositiveIntExpression | None
address_block_definition: Iterable[AddressBlockDefinition]
class org.accellera.ipxact.v1685_2022.AddressBlockRef(indices: org.accellera.ipxact.v1685_2022.indices.Indices | None = None, address_block_ref: str | None = None)

Bases: object

Parameters:

  • indices (Indices | None)

  • address_block_ref (str | None)

address_block_ref: str | None
indices: Indices | None
class org.accellera.ipxact.v1685_2022.AddressBlockType(name=None, display_name=None, short_description=None, description=None, access_handles=None, array=None, base_address=None, address_block_definition_ref=None, type_identifier=None, range=None, width=None, usage=None, volatile=None, access_policies=None, parameters=None, register=<factory>, register_file=<factory>, vendor_extensions=None, id=None, misalignment_allowed=True)

Bases: object

Top level address block that specify an address.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • array

  • base_address

  • address_block_definition_ref

  • type_identifier – Identifier name used to indicate that multiple addressBlock elements contain the exact same information except for the elements in the addressBlockInstanceGroup.

  • range – The address range of an address block. Expressed as the number of addressable units accessible to the block. The range and the width are related by the following formulas: number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range number_of_rows_in_block = number_of_bits_in_block / ipxact:width

  • width – The bit width of a row in the address block. The range and the width are related by the following formulas: number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range number_of_rows_in_block = number_of_bits_in_block / ipxact:width

  • usage – Indicates the usage of this block. Possible values are ‘memory’, ‘register’ and ‘reserved’.

  • volatile

  • access_policies

  • parameters – Any additional parameters needed to describe this address block to the generators.

  • register – A single register

  • register_file – A structure of registers and register files

  • vendor_extensions

  • id

  • misalignment_allowed – If true, register alignment is not restricted to register size. Defaults to false.

Parameters:
class AddressBlockDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
class Register(name=None, display_name=None, short_description=None, description=None, access_handles=None, array=None, address_offset=None, register_definition_ref=None, type_identifier=None, size=None, volatile=None, access_policies=None, field_value=<factory>, alternate_registers=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • array

  • address_offset – Offset from the address block’s baseAddress or the containing register file’s addressOffset, expressed as the number of addressUnitBits from the containing memoryMap or localMemoryMap.

  • register_definition_ref

  • type_identifier – Identifier name used to indicate that multiple register elements contain the exact same information for the elements in the registerDefinitionGroup.

  • size – Width of the register in bits.

  • volatile

  • access_policies

  • field_value – Describes individual bit fields within the register.

  • alternate_registers

  • parameters

  • vendor_extensions

  • id

Parameters:
class RegisterDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_offset: UnsignedLongintExpression | None
alternate_registers: AlternateRegisters | None
array: Array | None
description: Description | None
display_name: DisplayName | None
field_value: Iterable[FieldType]
id: str | None
name: str | None
parameters: Parameters | None
register_definition_ref: RegisterDefinitionRef | None
short_description: ShortDescription | None
size: UnsignedPositiveIntExpression | None
type_identifier: str | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_block_definition_ref: AddressBlockDefinitionRef | None
array: Array | None
base_address: BaseAddress | None
description: Description | None
display_name: DisplayName | None
id: str | None
misalignment_allowed: bool
name: str | None
parameters: Parameters | None
range: UnsignedPositiveLongintExpression | None
register: Iterable[Register]
register_file: Iterable[RegisterFile]
short_description: ShortDescription | None
type_identifier: str | None
usage: UsageType | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
width: UnsignedPositiveIntExpression | None
class org.accellera.ipxact.v1685_2022.AddressSpaces(address_space=<factory>)

Bases: object

If this component is a bus initiator, this lists all the address spaces defined by the component.

Variables:

address_space – This defines a logical space, referenced by a bus initiator.

Parameters:

address_space (Iterable[AddressSpace])

class AddressSpace(name=None, display_name=None, short_description=None, description=None, range=None, width=None, segments=None, address_unit_bits=None, local_memory_map=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • range – The address range of an address block. Expressed as the number of addressable units accessible to the block. The range and the width are related by the following formulas: number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range number_of_rows_in_block = number_of_bits_in_block / ipxact:width

  • width – The bit width of a row in the address block. The range and the width are related by the following formulas: number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range number_of_rows_in_block = number_of_bits_in_block / ipxact:width

  • segments – Address segments withing an addressSpace

  • address_unit_bits

  • local_memory_map – Provides the local memory map of an address space. Blocks in this memory map are accessable to initiator interfaces on this component that reference this address space. They are not accessable to any external initiator interface.

  • parameters – Data specific to this address space.

  • vendor_extensions

  • id

Parameters:
class Segments(segment=<factory>)

Bases: object

Variables:

segment – Address segment withing an addressSpace

Parameters:

segment (Iterable[Segment])

class Segment(name=None, display_name=None, short_description=None, description=None, address_offset=None, range=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • address_offset – Address offset of the segment within the containing address space.

  • range – The address range of asegment. Expressed as the number of addressable units accessible to the segment.

  • vendor_extensions

  • id

Parameters:
address_offset: UnsignedLongintExpression | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
range: UnsignedPositiveLongintExpression | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
segment: Iterable[Segment]
address_unit_bits: AddressUnitBits | None
description: Description | None
display_name: DisplayName | None
id: str | None
local_memory_map: LocalMemoryMapType | None
name: str | None
parameters: Parameters | None
range: UnsignedPositiveLongintExpression | None
segments: Segments | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
width: UnsignedPositiveIntExpression | None
address_space: Iterable[AddressSpace]
class org.accellera.ipxact.v1685_2022.AddressUnitBits(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: UnsignedPositiveLongintExpression

The number of data bits in an addressable unit.

The default is byte addressable (8 bits).

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.AlternateRegisterRef(alternate_register_ref: str | None = None)

Bases: object

Parameters:

alternate_register_ref (str | None)

alternate_register_ref: str | None
class org.accellera.ipxact.v1685_2022.AlternateRegisters(alternate_register=<factory>)

Bases: object

Alternate definitions for the current register.

Variables:

alternate_register – Alternate definition for the current register

Parameters:

alternate_register (Iterable[AlternateRegister])

class AlternateRegister(name=None, display_name=None, short_description=None, description=None, access_handles=None, mode_ref=<factory>, type_identifier=None, volatile=None, access_policies=None, field_value=<factory>, parameters=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • mode_ref

  • type_identifier – Identifier name used to indicate that multiple register elements contain the exact same information for the elements in the alternateRegisterDefinitionGroup.

  • volatile

  • access_policies

  • field_value – Describes individual bit fields within the register.

  • parameters

  • vendor_extensions

  • id

Parameters:
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
description: Description | None
display_name: DisplayName | None
field_value: Iterable[FieldType]
id: str | None
mode_ref: Iterable[ModeRef]
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
type_identifier: str | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
alternate_register: Iterable[AlternateRegister]
class org.accellera.ipxact.v1685_2022.AlwaysOn(value='', other_attributes=<factory>)

Bases: UnsignedBitExpression

Boolean value.

If set to true, then the domain/port is always powered, whatever its power domain. Only applies for output ports.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.Array(dim=<factory>, stride=None)

Bases: object

Variables:

  • dim – Dimensions a memory-map element array, the semantics for dim elements are the same as the C language standard for the layout of memory in multidimensional arrays.

  • stride

Parameters:
dim: Iterable[Dim]
stride: Stride | None
class org.accellera.ipxact.v1685_2022.Arrays(array=<factory>)

Bases: object

Variables:

array – Specific left and right array bounds.

Parameters:

array (Iterable[Array])

class Array(left: org.accellera.ipxact.v1685_2022.left.Left | None = None, right: org.accellera.ipxact.v1685_2022.right.Right | None = None, array_id: str | None = None, id: str | None = None)

Bases: object

Parameters:

  • left (Left | None)

  • right (Right | None)

  • array_id (str | None)

  • id (str | None)

array_id: str | None
id: str | None
left: Left | None
right: Right | None
array: Iterable[Array]
class org.accellera.ipxact.v1685_2022.Assertion(name=None, display_name=None, short_description=None, description=None, assert_value=None, id=None)

Bases: object

Provides an expression for describing valid parameter value settings.

If a assertion assert expression evaluates false, the name, displayName and/or description can be used to communicate the assertion failure.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • assert_value

  • id

Parameters:
assert_value: UnsignedBitExpression | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
class org.accellera.ipxact.v1685_2022.Assertions(assertion=<factory>)

Bases: object

List of assertions about allowed parameter values.

Parameters:

assertion (Iterable[Assertion])

assertion: Iterable[Assertion]
class org.accellera.ipxact.v1685_2022.BankAlignmentType(*values)

Bases: Enum

‘serial’ or ‘parallel’ bank alignment.

PARALLEL = 'parallel'
SERIAL = 'serial'
class org.accellera.ipxact.v1685_2022.BankDefinitions(bank_definition: collections.abc.Iterable['BankDefinitions.BankDefinition'] = <factory>)

Bases: object

Parameters:

bank_definition (Iterable[BankDefinition])

class BankDefinition(name=None, display_name=None, short_description=None, description=None, address_block=<factory>, bank=<factory>, usage=None, volatile=None, access_policies=None, parameters=None, address_unit_bits=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • address_block – An address block within the bank. No address information is supplied.

  • bank – A nested bank of blocks within a bank. No address information is supplied.

  • usage – Indicates the usage of this block. Possible values are ‘memory’, ‘register’ and ‘reserved’.

  • volatile

  • access_policies

  • parameters – Any additional parameters needed to describe this address block to the generators.

  • address_unit_bits

  • vendor_extensions

  • id

Parameters:
access_policies: AccessPolicies | None
address_block: Iterable[BankedBlockType]
address_unit_bits: AddressUnitBits | None
bank: Iterable[Bank]
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
usage: UsageType | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
bank_definition: Iterable[BankDefinition]
class org.accellera.ipxact.v1685_2022.BankRef(bank_ref: str | None = None, id: str | None = None)

Bases: object

Parameters:

  • bank_ref (str | None)

  • id (str | None)

bank_ref: str | None
id: str | None
class org.accellera.ipxact.v1685_2022.BankedBankType(name=None, display_name=None, short_description=None, description=None, access_handles=None, bank_definition_ref=None, address_block=<factory>, bank=<factory>, subspace_map=<factory>, usage=None, volatile=None, access_policies=None, parameters=None, bank_alignment=None, id=None)

Bases: object

Banks nested inside a bank do not specify address.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • bank_definition_ref

  • address_block – An address block within the bank. No address information is supplied.

  • bank – A nested bank of blocks within a bank. No address information is supplied.

  • subspace_map – A subspace map within the bank. No address information is supplied.

  • usage – Indicates the usage of this block. Possible values are ‘memory’, ‘register’ and ‘reserved’.

  • volatile

  • access_policies

  • parameters – Any additional parameters needed to describe this address block to the generators.

  • bank_alignment

  • id

Parameters:
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_block: Iterable[BankedBlockType]
bank: Iterable[Bank]
bank_alignment: BankAlignmentType | None
bank_definition_ref: BankDefinitionRef | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
subspace_map: Iterable[BankedSubspaceType]
usage: UsageType | None
volatile: Volatile | None
class org.accellera.ipxact.v1685_2022.BankedBlockType(name=None, display_name=None, short_description=None, description=None, access_handles=None, range=None, width=None, usage=None, volatile=None, access_policies=None, parameters=None, register=<factory>, register_file=<factory>, vendor_extensions=None, id=None)

Bases: object

Address blocks inside a bank do not specify address.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • range – The address range of an address block. Expressed as the number of addressable units accessible to the block. The range and the width are related by the following formulas: number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range number_of_rows_in_block = number_of_bits_in_block / ipxact:width

  • width – The bit width of a row in the address block. The range and the width are related by the following formulas: number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range number_of_rows_in_block = number_of_bits_in_block / ipxact:width

  • usage – Indicates the usage of this block. Possible values are ‘memory’, ‘register’ and ‘reserved’.

  • volatile

  • access_policies

  • parameters – Any additional parameters needed to describe this address block to the generators.

  • register – A single register

  • register_file – A structure of registers and register files

  • vendor_extensions

  • id

Parameters:
class Register(name=None, display_name=None, short_description=None, description=None, access_handles=None, array=None, address_offset=None, register_definition_ref=None, type_identifier=None, size=None, volatile=None, access_policies=None, field_value=<factory>, alternate_registers=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • array

  • address_offset – Offset from the address block’s baseAddress or the containing register file’s addressOffset, expressed as the number of addressUnitBits from the containing memoryMap or localMemoryMap.

  • register_definition_ref

  • type_identifier – Identifier name used to indicate that multiple register elements contain the exact same information for the elements in the registerDefinitionGroup.

  • size – Width of the register in bits.

  • volatile

  • access_policies

  • field_value – Describes individual bit fields within the register.

  • alternate_registers

  • parameters

  • vendor_extensions

  • id

Parameters:
class RegisterDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_offset: UnsignedLongintExpression | None
alternate_registers: AlternateRegisters | None
array: Array | None
description: Description | None
display_name: DisplayName | None
field_value: Iterable[FieldType]
id: str | None
name: str | None
parameters: Parameters | None
register_definition_ref: RegisterDefinitionRef | None
short_description: ShortDescription | None
size: UnsignedPositiveIntExpression | None
type_identifier: str | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
range: UnsignedPositiveLongintExpression | None
register: Iterable[Register]
register_file: Iterable[RegisterFile]
short_description: ShortDescription | None
usage: UsageType | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
width: UnsignedPositiveIntExpression | None
class org.accellera.ipxact.v1685_2022.BankedDefinitionBankType(name=None, display_name=None, short_description=None, description=None, access_handles=None, bank_definition_ref=None, address_block=<factory>, bank=<factory>, usage=None, volatile=None, access_policies=None, parameters=None, bank_alignment=None, id=None)

Bases: object

Banks nested inside a bank do not specify address.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • bank_definition_ref

  • address_block – An address block within the bank. No address information is supplied.

  • bank – A nested bank of blocks within a bank. No address information is supplied.

  • usage – Indicates the usage of this block. Possible values are ‘memory’, ‘register’ and ‘reserved’.

  • volatile

  • access_policies

  • parameters – Any additional parameters needed to describe this address block to the generators.

  • bank_alignment

  • id

Parameters:
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_block: Iterable[BankedBlockType]
bank: Iterable[Bank]
bank_alignment: BankAlignmentType | None
bank_definition_ref: BankDefinitionRef | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
usage: UsageType | None
volatile: Volatile | None
class org.accellera.ipxact.v1685_2022.BankedSubspaceType(name=None, display_name=None, short_description=None, description=None, parameters=None, vendor_extensions=None, initiator_ref=None, id=None)

Bases: object

Subspace references inside banks do not specify an address.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • parameters – Any parameters that may apply to the subspace reference.

  • vendor_extensions

  • initiator_ref – For subspaceMap elements, this attribute identifies the initiator that contains the address space to be mapped.

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
id: str | None
initiator_ref: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.BaseAddress(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: UnsignedLongintExpression

Base of an address block, bank or address space.

Expressed as the number of addressable units from the containing memoryMap or localMemoryMap.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.BitStride(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[int] = None, maximum: Optional[int] = None, id: Optional[str] = None)

Bases: UnsignedPositiveLongintExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

  • id (str | None)

id: str | None
maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.BitsInLau(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: UnsignedPositiveLongintExpression

The number of bits in the least addressable unit.

The default is byte addressable (8 bits).

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.BusDefinition(vendor=None, library=None, name=None, version=None, display_name=None, short_description=None, description=None, direct_connection=None, broadcast=None, is_addressable=None, extends=None, max_initiators=None, max_targets=None, system_group_names=None, choices=None, parameters=None, assertions=None, vendor_extensions=None, id=None)

Bases: object

Defines the structural information associated with a bus type, independent of the abstraction level.

Variables:

  • vendor – Name of the vendor who supplies this file.

  • library – Name of the logical library this element belongs to.

  • name – The name of the object.

  • version – Indicates the version of the named element.

  • display_name – Name for display purposes. Typically a few words providing a more detailed and/or user-friendly name than the vlnv.

  • short_description

  • description

  • direct_connection – This element indicates that a initiator interface may be directly connected to a target interface (under certain conditions) for busses of this type.

  • broadcast – This element indicates that this bus definition supports ‘broadcast’ mode. This means that it is legal to make one-to-many interface connections.

  • is_addressable – If true, indicates that this is an addressable bus.

  • extends – Optional name of bus type that this bus definition is compatible with. This bus definition may change the definitions in the existing bus definition

  • max_initiators – Indicates the maximum number of initiators this bus supports. If this element is not present, the number of initiators allowed is unbounded.

  • max_targets – Indicates the maximum number of targets this bus supports. If the element is not present, the number of targets allowed is unbounded.

  • system_group_names – Indicates the list of system group names that are defined for this bus definition.

  • choices

  • parameters

  • assertions

  • vendor_extensions

  • id

Parameters:
class SystemGroupNames(system_group_name=<factory>)

Bases: object

Variables:

system_group_name – Indicates the name of a system group defined for this bus definition.

Parameters:

system_group_name (Iterable[SystemGroupName])

class SystemGroupName(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
system_group_name: Iterable[SystemGroupName]
assertions: Assertions | None
broadcast: bool | None
choices: Choices | None
description: Description | None
direct_connection: bool | None
display_name: str | None
extends: LibraryRefType | None
id: str | None
is_addressable: bool | None
library: str | None
max_initiators: UnsignedIntExpression | None
max_targets: UnsignedIntExpression | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
system_group_names: SystemGroupNames | None
vendor: str | None
vendor_extensions: VendorExtensions | None
version: str | None
class org.accellera.ipxact.v1685_2022.BusInterface(name=None, display_name=None, short_description=None, description=None, bus_type=None, abstraction_types=None, initiator=None, target=None, system=None, mirrored_target=None, mirrored_initiator=None, mirrored_system=None, monitor=None, connection_required=None, bits_in_lau=None, bit_steering=None, endianness=None, parameters=None, vendor_extensions=None, id=None, other_attributes=<factory>)

Bases: BusInterfaceType

Describes one of the bus interfaces supported by this component.

Parameters:
class Initiator(address_space_ref=None)

Bases: object

Variables:

address_space_ref – If this initiator connects to an addressable bus, this element references the address space it maps to.

Parameters:

address_space_ref (AddressSpaceRef | None)

class AddressSpaceRef(vendor_extensions=None, address_space_ref=None, id=None, base_address=None, mode_ref=<factory>)

Bases: AddrSpaceRefType

Variables:

  • base_address – Base of an address space.

  • mode_ref

Parameters:
class ModeRef(value='', id=None)

Bases: object

A reference to a mode.

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
address_space_ref: str | None
base_address: SignedLongintExpression | None
id: str | None
mode_ref: Iterable[ModeRef]
vendor_extensions: VendorExtensions | None
address_space_ref: AddressSpaceRef | None
class MirroredSystem(group: org.accellera.ipxact.v1685_2022.group.Group | None = None)

Bases: object

Parameters:

group (Group | None)

group: Group | None
class MirroredTarget(base_addresses=None)

Bases: object

Variables:

base_addresses – Represents a set of remap base addresses.

Parameters:

base_addresses (BaseAddresses | None)

class BaseAddresses(remap_addresses=<factory>, range=None)

Bases: object

Variables:

  • remap_addresses

  • range – The address range of mirrored target, expressed as the number of bitsInLAU from the containing busInterface.

Parameters:
class RemapAddresses(remap_address=None, mode_ref=<factory>, id=None)

Bases: object

Variables:

  • remap_address – Base of an address block, expressed as the number of bitsInLAU from the containing busInterface. The modeRef element indicates the name of the mode for which this address is valid.

  • mode_ref

  • id

Parameters:
id: str | None
mode_ref: Iterable[ModeRef]
remap_address: UnsignedLongintExpression | None
range: UnsignedPositiveLongintExpression | None
remap_addresses: Iterable[RemapAddresses]
base_addresses: BaseAddresses | None
class Monitor(group=None, interface_mode=None)

Bases: object

Variables:

  • group – Indicates which system interface is being monitored. Name must match a group name present on one or more ports in the corresonding bus definition.

  • interface_mode

Parameters:
group: Group | None
interface_mode: MonitorInterfaceMode | None
class System(group: org.accellera.ipxact.v1685_2022.group.Group | None = None)

Bases: object

Parameters:

group (Group | None)

group: Group | None
class Target(memory_map_ref=None, transparent_bridge=<factory>, file_set_ref_group=<factory>)

Bases: object

Variables:

  • memory_map_ref

  • transparent_bridge

  • file_set_ref_group – This reference is used to point the filesets that are associated with this target port. Depending on the target port function, there may be completely different software drivers associated with the different ports.

Parameters:
class FileSetRefGroup(group=None, file_set_ref=<factory>, id=None)

Bases: object

Variables:

  • group – Abritray name assigned to the collections of fileSets.

  • file_set_ref

  • id

Parameters:

  • group (str | None)

  • file_set_ref (Iterable[FileSetRef])

  • id (str | None)

file_set_ref: Iterable[FileSetRef]
group: str | None
id: str | None
file_set_ref_group: Iterable[FileSetRefGroup]
memory_map_ref: MemoryMapRef | None
transparent_bridge: Iterable[TransparentBridge]
abstraction_types: AbstractionTypes | None
bit_steering: UnsignedBitExpression | None
bits_in_lau: BitsInLau | None
bus_type: ConfigurableLibraryRefType | None
connection_required: bool | None
description: Description | None
display_name: DisplayName | None
endianness: EndianessType | None
id: str | None
initiator: 'BusInterfaceType.Initiator' | None
mirrored_initiator: object | None
mirrored_system: 'BusInterfaceType.MirroredSystem' | None
mirrored_target: 'BusInterfaceType.MirroredTarget' | None
monitor: 'BusInterfaceType.Monitor' | None
name: str | None
other_attributes: Mapping[str, str]
parameters: Parameters | None
short_description: ShortDescription | None
system: 'BusInterfaceType.System' | None
target: 'BusInterfaceType.Target' | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.BusInterfaceType(name=None, display_name=None, short_description=None, description=None, bus_type=None, abstraction_types=None, initiator=None, target=None, system=None, mirrored_target=None, mirrored_initiator=None, mirrored_system=None, monitor=None, connection_required=None, bits_in_lau=None, bit_steering=None, endianness=None, parameters=None, vendor_extensions=None, id=None, other_attributes=<factory>)

Bases: object

Type definition for a busInterface in a component.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • bus_type – The bus type of this interface. Refers to bus definition using vendor, library, name, version attributes along with any configurable element values needed to configure this interface.

  • abstraction_types

  • initiator – If this element is present, the bus interface can serve as a initiator. This element encapsulates additional information related to its role as initiator.

  • target – If this element is present, the bus interface can serve as a target.

  • system – If this element is present, the bus interface is a system interface, neither initiator nor target, with a specific function on the bus.

  • mirrored_target – If this element is present, the bus interface represents a mirrored target interface. All directional constraints on ports are reversed relative to the specification in the bus definition.

  • mirrored_initiator – If this element is present, the bus interface represents a mirrored initiator interface. All directional constraints on ports are reversed relative to the specification in the bus definition.

  • mirrored_system – If this element is present, the bus interface represents a mirrored system interface. All directional constraints on ports are reversed relative to the specification in the bus definition.

  • monitor – Indicates that this is a (passive) monitor interface. All of the ports in the interface must be inputs. The type of interface to be monitored is specified with the required interfaceType attribute. The ipxact:group element must be specified if monitoring a system interface.

  • connection_required – Indicates whether a connection to this interface is required for proper component functionality.

  • bits_in_lau

  • bit_steering – Indicates whether bit steering should be used to map this interface onto a bus of different data width. Values are “0”, “1” (defaults to “0”).

  • endianness – ‘big’: means the most significant element of any multi-element data field is stored at the lowest memory address. ‘little’ means the least significant element of any multi-element data field is stored at the lowest memory address. If this element is not present the default is ‘little’ endian.

  • parameters

  • vendor_extensions

  • id

  • other_attributes

Parameters:
class Initiator(address_space_ref=None)

Bases: object

Variables:

address_space_ref – If this initiator connects to an addressable bus, this element references the address space it maps to.

Parameters:

address_space_ref (AddressSpaceRef | None)

class AddressSpaceRef(vendor_extensions=None, address_space_ref=None, id=None, base_address=None, mode_ref=<factory>)

Bases: AddrSpaceRefType

Variables:

  • base_address – Base of an address space.

  • mode_ref

Parameters:
class ModeRef(value='', id=None)

Bases: object

A reference to a mode.

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
address_space_ref: str | None
base_address: SignedLongintExpression | None
id: str | None
mode_ref: Iterable[ModeRef]
vendor_extensions: VendorExtensions | None
address_space_ref: AddressSpaceRef | None
class MirroredSystem(group: org.accellera.ipxact.v1685_2022.group.Group | None = None)

Bases: object

Parameters:

group (Group | None)

group: Group | None
class MirroredTarget(base_addresses=None)

Bases: object

Variables:

base_addresses – Represents a set of remap base addresses.

Parameters:

base_addresses (BaseAddresses | None)

class BaseAddresses(remap_addresses=<factory>, range=None)

Bases: object

Variables:

  • remap_addresses

  • range – The address range of mirrored target, expressed as the number of bitsInLAU from the containing busInterface.

Parameters:
class RemapAddresses(remap_address=None, mode_ref=<factory>, id=None)

Bases: object

Variables:

  • remap_address – Base of an address block, expressed as the number of bitsInLAU from the containing busInterface. The modeRef element indicates the name of the mode for which this address is valid.

  • mode_ref

  • id

Parameters:
id: str | None
mode_ref: Iterable[ModeRef]
remap_address: UnsignedLongintExpression | None
range: UnsignedPositiveLongintExpression | None
remap_addresses: Iterable[RemapAddresses]
base_addresses: BaseAddresses | None
class Monitor(group=None, interface_mode=None)

Bases: object

Variables:

  • group – Indicates which system interface is being monitored. Name must match a group name present on one or more ports in the corresonding bus definition.

  • interface_mode

Parameters:
group: Group | None
interface_mode: MonitorInterfaceMode | None
class System(group: org.accellera.ipxact.v1685_2022.group.Group | None = None)

Bases: object

Parameters:

group (Group | None)

group: Group | None
class Target(memory_map_ref=None, transparent_bridge=<factory>, file_set_ref_group=<factory>)

Bases: object

Variables:

  • memory_map_ref

  • transparent_bridge

  • file_set_ref_group – This reference is used to point the filesets that are associated with this target port. Depending on the target port function, there may be completely different software drivers associated with the different ports.

Parameters:
class FileSetRefGroup(group=None, file_set_ref=<factory>, id=None)

Bases: object

Variables:

  • group – Abritray name assigned to the collections of fileSets.

  • file_set_ref

  • id

Parameters:

  • group (str | None)

  • file_set_ref (Iterable[FileSetRef])

  • id (str | None)

file_set_ref: Iterable[FileSetRef]
group: str | None
id: str | None
file_set_ref_group: Iterable[FileSetRefGroup]
memory_map_ref: MemoryMapRef | None
transparent_bridge: Iterable[TransparentBridge]
abstraction_types: AbstractionTypes | None
bit_steering: UnsignedBitExpression | None
bits_in_lau: BitsInLau | None
bus_type: ConfigurableLibraryRefType | None
connection_required: bool | None
description: Description | None
display_name: DisplayName | None
endianness: EndianessType | None
id: str | None
initiator: Initiator | None
mirrored_initiator: object | None
mirrored_system: MirroredSystem | None
mirrored_target: MirroredTarget | None
monitor: Monitor | None
name: str | None
other_attributes: Mapping[str, str]
parameters: Parameters | None
short_description: ShortDescription | None
system: System | None
target: Target | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.BusInterfaces(bus_interface=<factory>)

Bases: object

A list of bus interfaces supported by this component.

Parameters:

bus_interface (Iterable[BusInterface])

bus_interface: Iterable[BusInterface]
class org.accellera.ipxact.v1685_2022.BusWidth(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: UnsignedIntExpression

Defines the bus size in bits.

This can be the result of an expression.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.Catalog(vendor=None, library=None, name=None, version=None, display_name=None, short_description=None, description=None, catalogs=None, bus_definitions=None, abstraction_definitions=None, components=None, abstractors=None, designs=None, design_configurations=None, generator_chains=None, type_definitions=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • vendor – Name of the vendor who supplies this file.

  • library – Name of the logical library this element belongs to.

  • name – The name of the object.

  • version – Indicates the version of the named element.

  • display_name – Name for display purposes. Typically a few words providing a more detailed and/or user-friendly name than the vlnv.

  • short_description

  • description

  • catalogs

  • bus_definitions

  • abstraction_definitions

  • components

  • abstractors

  • designs

  • design_configurations

  • generator_chains

  • type_definitions

  • vendor_extensions

  • id

Parameters:
abstraction_definitions: IpxactFilesType | None
abstractors: IpxactFilesType | None
bus_definitions: IpxactFilesType | None
catalogs: IpxactFilesType | None
components: IpxactFilesType | None
description: Description | None
design_configurations: IpxactFilesType | None
designs: IpxactFilesType | None
display_name: str | None
generator_chains: IpxactFilesType | None
id: str | None
library: str | None
name: str | None
short_description: ShortDescription | None
type_definitions: IpxactFilesType | None
vendor: str | None
vendor_extensions: VendorExtensions | None
version: str | None
class org.accellera.ipxact.v1685_2022.CellClassValueType(*values)

Bases: Enum

Indicates legal cell class values.

COMBINATIONAL = 'combinational'
SEQUENTIAL = 'sequential'
class org.accellera.ipxact.v1685_2022.CellFunctionValueType(*values)

Bases: Enum

Indicates legal cell function values.

BUF = 'buf'
DFF = 'dff'
INV = 'inv'
LATCH = 'latch'
MUX21 = 'mux21'
NAND2 = 'nand2'
OTHER = 'other'
XOR2 = 'xor2'
class org.accellera.ipxact.v1685_2022.CellSpecification(cell_function=None, cell_class=None, cell_strength=None)

Bases: object

Used to provide a generic description of a technology library cell.

Variables:

  • cell_function – Defines a technology library cell in library independent fashion, based on specification of a cell function and strength.

  • cell_class – Defines a technology library cell in library independent fashion, based on specification of a cell class and strength.

  • cell_strength – Indicates the desired strength of the specified cell.

Parameters:
class CellFunction(value: org.accellera.ipxact.v1685_2022.cell_function_value_type.CellFunctionValueType | None = None, other: str | None = None)

Bases: object

Parameters:
other: str | None
value: CellFunctionValueType | None
cell_class: CellClassValueType | None
cell_function: CellFunction | None
cell_strength: CellStrengthValueType | None
class org.accellera.ipxact.v1685_2022.CellStrengthValueType(*values)

Bases: Enum

Indicates legal cell strength values.

HIGH = 'high'
LOW = 'low'
MEDIAN = 'median'
class org.accellera.ipxact.v1685_2022.Channels(channel=<factory>)

Bases: object

Lists all channel connections between mirror interfaces of this component.

Variables:

channel – Defines a set of mirrored interfaces of this component that are connected to one another.

Parameters:

channel (Iterable[Channel])

class Channel(name=None, display_name=None, short_description=None, description=None, bus_interface_ref=<factory>, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • bus_interface_ref – Contains the name of one of the bus interfaces that is part of this channel. The ordering of the references may be important to the design environment.

  • vendor_extensions

  • id

Parameters:
class BusInterfaceRef(local_name: str | None = None, vendor_extensions: org.accellera.ipxact.v1685_2022.vendor_extensions.VendorExtensions | None = None, id: str | None = None)

Bases: object

Parameters:

  • local_name (str | None)

  • vendor_extensions (VendorExtensions | None)

  • id (str | None)

id: str | None
local_name: str | None
vendor_extensions: VendorExtensions | None
bus_interface_ref: Iterable[BusInterfaceRef]
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
channel: Iterable[Channel]
class org.accellera.ipxact.v1685_2022.Choices(choice=<factory>)

Bases: object

Choices used by elements with an attribute ipxact:choiceRef.

Variables:

choice – Non-empty set of legal values for a elements with an attribute ipxact:choiceRef.

Parameters:

choice (Iterable[Choice])

class Choice(name=None, enumeration=<factory>, id=None)

Bases: object

Variables:

  • name – Choice key, available for reference by the ipxact:choiceRef attribute.

  • enumeration – One possible value of ipxact:choice

  • id

Parameters:

  • name (str | None)

  • enumeration (Iterable[Enumeration])

  • id (str | None)

class Enumeration(value='', other_attributes=<factory>, text=None, help=None, id=None)

Bases: ComplexBaseExpression

Variables:

  • text – When specified, displayed in place of the ipxact:enumeration value

  • help – Text that may be displayed if the user requests help about the meaning of an element

  • id

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • text (str | None)

  • help (str | None)

  • id (str | None)

help: str | None
id: str | None
other_attributes: Mapping[str, str]
text: str | None
value: str
enumeration: Iterable[Enumeration]
id: str | None
name: str | None
choice: Iterable[Choice]
class org.accellera.ipxact.v1685_2022.ClearboxElementRefType(location=<factory>, vendor_extensions=None, name=None, id=None)

Bases: object

Reference to a clearboxElement within a view.

The ‘name’ attribute must refer to a clearboxElement defined within this component.

Variables:

  • location – The contents of each location element can be used to specified one location (HDL Path) through the referenced clearBoxElement is accessible.

  • vendor_extensions

  • name – Reference to a clearboxElement defined within this component.

  • id

Parameters:
id: str | None
location: Iterable[SlicesType]
name: str | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.ClearboxElementType(name=None, display_name=None, short_description=None, description=None, clearbox_type=None, driveable=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Defines a clear box reference point within the component.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • clearbox_type – Indicates the type of the element. The pin and signal types refer to elements within the HDL description. The interface type refers to a group of signals addressed as a single unit.

  • driveable – If true, indicates that the clear box element can be driven (e.g. have a new value forced into it).

  • parameters

  • vendor_extensions

  • id

Parameters:
clearbox_type: SimpleClearboxType | None
description: Description | None
display_name: DisplayName | None
driveable: bool | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.ClockDriver(clock_period=None, clock_pulse_offset=None, clock_pulse_value=None, clock_pulse_duration=None, id=None, clock_name=None)

Bases: ClockDriverType

Describes a driven clock port.

Variables:

clock_name – Indicates the name of the cllock. If not specified the name is assumed to be the name of the containing port.

Parameters:
class ClockPeriod(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[float] = None, maximum: Optional[float] = None, units: org.accellera.ipxact.v1685_2022.delay_value_unit_type.DelayValueUnitType = <DelayValueUnitType.NS: 'ns'>)

Bases: RealExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

  • units (DelayValueUnitType)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
units: DelayValueUnitType
value: str
class ClockPulseDuration(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[float] = None, maximum: Optional[float] = None, units: org.accellera.ipxact.v1685_2022.delay_value_unit_type.DelayValueUnitType = <DelayValueUnitType.NS: 'ns'>)

Bases: RealExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

  • units (DelayValueUnitType)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
units: DelayValueUnitType
value: str
class ClockPulseOffset(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[float] = None, maximum: Optional[float] = None, units: org.accellera.ipxact.v1685_2022.delay_value_unit_type.DelayValueUnitType = <DelayValueUnitType.NS: 'ns'>)

Bases: RealExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

  • units (DelayValueUnitType)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
units: DelayValueUnitType
value: str
clock_name: str | None
clock_period: 'ClockDriverType.ClockPeriod' | None
clock_pulse_duration: 'ClockDriverType.ClockPulseDuration' | None
clock_pulse_offset: 'ClockDriverType.ClockPulseOffset' | None
clock_pulse_value: UnsignedBitExpression | None
id: str | None
class org.accellera.ipxact.v1685_2022.ClockDriverType(clock_period=None, clock_pulse_offset=None, clock_pulse_value=None, clock_pulse_duration=None, id=None)

Bases: object

Variables:

  • clock_period – Clock period in units defined by the units attribute. Default is nanoseconds.

  • clock_pulse_offset – Time until first pulse. Units are defined by the units attribute. Default is nanoseconds.

  • clock_pulse_value – Value of port after first clock edge.

  • clock_pulse_duration – Duration of first state in cycle. Units are defined by the units attribute. Default is nanoseconds.

  • id

Parameters:
class ClockPeriod(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[float] = None, maximum: Optional[float] = None, units: org.accellera.ipxact.v1685_2022.delay_value_unit_type.DelayValueUnitType = <DelayValueUnitType.NS: 'ns'>)

Bases: RealExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

  • units (DelayValueUnitType)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
units: DelayValueUnitType
value: str
class ClockPulseDuration(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[float] = None, maximum: Optional[float] = None, units: org.accellera.ipxact.v1685_2022.delay_value_unit_type.DelayValueUnitType = <DelayValueUnitType.NS: 'ns'>)

Bases: RealExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

  • units (DelayValueUnitType)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
units: DelayValueUnitType
value: str
class ClockPulseOffset(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[float] = None, maximum: Optional[float] = None, units: org.accellera.ipxact.v1685_2022.delay_value_unit_type.DelayValueUnitType = <DelayValueUnitType.NS: 'ns'>)

Bases: RealExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

  • units (DelayValueUnitType)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
units: DelayValueUnitType
value: str
clock_period: ClockPeriod | None
clock_pulse_duration: ClockPulseDuration | None
clock_pulse_offset: ClockPulseOffset | None
clock_pulse_value: UnsignedBitExpression | None
id: str | None
class org.accellera.ipxact.v1685_2022.ComplexBaseExpression(value='', other_attributes=<factory>)

Bases: object

Represents the base-type for an expressions.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.ComplexTiedValueExpression(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: object

An unsigned bit vector expression that resolves to the value set {0, 1, …} or or the string values ‘open’ or ‘default’.

It is derived from simpleUnsignedBitVectorExpression and it supports an expression value.

Variables:

  • value

  • other_attributes

  • minimum – For elements which can be specified using expression which are supposed to be resolved to a long value, this indicates the minimum value allowed.

  • maximum – For elements which can be specified using expression which are supposed to be resolved to a long value, this indicates the maximum value allowed.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.Component(vendor=None, library=None, name=None, version=None, display_name=None, short_description=None, description=None, type_definitions=None, power_domains=None, bus_interfaces=None, indirect_interfaces=None, channels=None, modes=None, address_spaces=None, memory_maps=None, model=None, component_generators=None, choices=None, file_sets=None, clearbox_elements=None, cpus=None, other_clock_drivers=None, reset_types=None, parameters=None, assertions=None, vendor_extensions=None, id=None)

Bases: ComponentType

This is the root element for all non platform-core components.

Parameters:
class ClearboxElements(clearbox_element=<factory>)

Bases: object

Variables:

clearbox_element – A clearboxElement is a useful way to identify elements of a component that can not be identified through other means such as internal signals and non- software accessible registers.

Parameters:

clearbox_element (Iterable[ClearboxElementType])

clearbox_element: Iterable[ClearboxElementType]
class Cpus(cpu=<factory>)

Bases: object

Variables:

cpu – Describes a processor in this component.

Parameters:

cpu (Iterable[Cpu])

class Cpu(name=None, display_name=None, short_description=None, description=None, range=None, width=None, regions=None, address_unit_bits=None, executable_image=<factory>, memory_map_ref=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • range – The address range of an address block. Expressed as the number of addressable units accessible to the block. The range and the width are related by the following formulas: number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range number_of_rows_in_block = number_of_bits_in_block / ipxact:width

  • width – The bit width of a row in the address block. The range and the width are related by the following formulas: number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range number_of_rows_in_block = number_of_bits_in_block / ipxact:width

  • regions – Address regions within a cpu system address map.

  • address_unit_bits

  • executable_image

  • memory_map_ref – Indicates which memory maps into this cpu.

  • parameters – Data specific to the cpu.

  • vendor_extensions

  • id

Parameters:
class Regions(region=<factory>)

Bases: object

Variables:

region – Address region within a system address map.

Parameters:

region (Iterable[Region])

class Region(name=None, display_name=None, short_description=None, description=None, address_offset=None, range=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • address_offset – Address offset of the region within the system address map.

  • range – The address range of region. Expressed as the number of addressable units accessible to the region.

  • vendor_extensions

  • id

Parameters:
address_offset: UnsignedLongintExpression | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
range: UnsignedPositiveLongintExpression | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
region: Iterable[Region]
address_unit_bits: AddressUnitBits | None
description: Description | None
display_name: DisplayName | None
executable_image: Iterable[ExecutableImage]
id: str | None
memory_map_ref: str | None
name: str | None
parameters: Parameters | None
range: UnsignedPositiveLongintExpression | None
regions: Regions | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
width: UnsignedPositiveIntExpression | None
cpu: Iterable[Cpu]
class Modes(mode: collections.abc.Iterable['ComponentType.Modes.Mode'] = <factory>)

Bases: object

Parameters:

mode (Iterable[Mode])

class Mode(name=None, display_name=None, short_description=None, description=None, port_slice=<factory>, field_slice=<factory>, condition=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • port_slice

  • field_slice – Reference to a register field slice

  • condition

  • vendor_extensions

  • id

Parameters:
class FieldSlice(name=None, display_name=None, short_description=None, description=None, address_space_ref=None, memory_map_ref=None, memory_remap_ref=None, bank_ref=<factory>, address_block_ref=None, register_file_ref=<factory>, register_ref=None, alternate_register_ref=None, field_ref=None, range=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • address_space_ref

  • memory_map_ref

  • memory_remap_ref

  • bank_ref

  • address_block_ref

  • register_file_ref

  • register_ref

  • alternate_register_ref

  • field_ref

  • range

  • id

Parameters:
class AddressSpaceRef(address_space_ref: str | None = None)

Bases: object

Parameters:

address_space_ref (str | None)

address_space_ref: str | None
class MemoryMapRef(memory_map_ref: str | None = None)

Bases: object

Parameters:

memory_map_ref (str | None)

memory_map_ref: str | None
address_block_ref: AddressBlockRef | None
address_space_ref: AddressSpaceRef | None
alternate_register_ref: AlternateRegisterRef | None
bank_ref: Iterable[BankRef]
description: Description | None
display_name: DisplayName | None
field_ref: FieldRef | None
id: str | None
memory_map_ref: MemoryMapRef | None
memory_remap_ref: MemoryRemapRef | None
name: str | None
range: Range | None
register_file_ref: Iterable[RegisterFileRef]
register_ref: RegisterRef | None
short_description: ShortDescription | None
class PortSlice(name=None, display_name=None, short_description=None, description=None, port_ref=None, sub_port_reference=<factory>, part_select=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • port_ref

  • sub_port_reference

  • part_select

  • id

Parameters:
class PortRef(port_ref: str | None = None)

Bases: object

Parameters:

port_ref (str | None)

port_ref: str | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
part_select: PartSelect | None
port_ref: PortRef | None
short_description: ShortDescription | None
sub_port_reference: Iterable[SubPortReference]
condition: UnresolvedUnsignedBitExpression | None
description: Description | None
display_name: DisplayName | None
field_slice: Iterable[FieldSlice]
id: str | None
name: str | None
port_slice: Iterable[PortSlice]
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
mode: Iterable[Mode]
class PowerDomains(power_domain: collections.abc.Iterable['ComponentType.PowerDomains.PowerDomain'] = <factory>)

Bases: object

Parameters:

power_domain (Iterable[PowerDomain])

class PowerDomain(name=None, display_name=None, short_description=None, description=None, always_on=None, sub_domain_of=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • always_on

  • sub_domain_of – Reference to a power domain defined on this component

  • parameters

  • vendor_extensions

  • id

Parameters:
always_on: AlwaysOn | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
sub_domain_of: str | None
vendor_extensions: VendorExtensions | None
power_domain: Iterable[PowerDomain]
class ResetTypes(reset_type=<factory>)

Bases: object

Variables:

reset_type – A user defined reset policy

Parameters:

reset_type (Iterable[ResetType])

class ResetType(name=None, display_name=None, short_description=None, description=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • vendor_extensions

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
reset_type: Iterable[ResetType]
class TypeDefinitions(external_type_definitions: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.external_type_definitions.ExternalTypeDefinitions] = <factory>)

Bases: object

Parameters:

external_type_definitions (Iterable[ExternalTypeDefinitions])

external_type_definitions: Iterable[ExternalTypeDefinitions]
address_spaces: AddressSpaces | None
assertions: Assertions | None
bus_interfaces: BusInterfaces | None
channels: Channels | None
choices: Choices | None
clearbox_elements: 'ComponentType.ClearboxElements' | None
component_generators: ComponentGenerators | None
cpus: 'ComponentType.Cpus' | None
description: Description | None
display_name: str | None
file_sets: FileSets | None
id: str | None
indirect_interfaces: IndirectInterfaces | None
library: str | None
memory_maps: MemoryMaps | None
model: Model | None
modes: 'ComponentType.Modes' | None
name: str | None
other_clock_drivers: OtherClocks | None
parameters: Parameters | None
power_domains: 'ComponentType.PowerDomains' | None
reset_types: 'ComponentType.ResetTypes' | None
short_description: ShortDescription | None
type_definitions: 'ComponentType.TypeDefinitions' | None
vendor: str | None
vendor_extensions: VendorExtensions | None
version: str | None
class org.accellera.ipxact.v1685_2022.ComponentGenerator(name=None, display_name=None, short_description=None, description=None, phase=None, parameters=None, api_type=None, api_service=None, transport_methods=None, generator_exe=None, vendor_extensions=None, hidden=False, id=None, group=<factory>, scope=InstanceGeneratorTypeScope.INSTANCE)

Bases: InstanceGeneratorType

Specifies a set of component generators.

The scope attribute applies to component generators and specifies whether the generator should be run for each instance of the entity (or module) or just once for all instances of the entity.

Parameters:
api_service: GeneratorTypeApiService | None
api_type: 'GeneratorType.ApiType' | None
description: Description | None
display_name: DisplayName | None
generator_exe: IpxactUri | None
group: Iterable['InstanceGeneratorType.Group']
hidden: bool
id: str | None
name: str | None
parameters: Parameters | None
phase: Phase | None
scope: InstanceGeneratorTypeScope
short_description: ShortDescription | None
transport_methods: 'GeneratorType.TransportMethods' | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.ComponentGenerators(component_generator=<factory>)

Bases: object

List of component generators.

Parameters:

component_generator (Iterable[ComponentGenerator])

component_generator: Iterable[ComponentGenerator]
class org.accellera.ipxact.v1685_2022.ComponentInstance(instance_name=None, display_name=None, short_description=None, description=None, component_ref=None, power_domain_links=None, vendor_extensions=None, id=None)

Bases: object

Component instance element.

The instance name is contained in the unique-value instanceName attribute.

Variables:

  • instance_name

  • display_name

  • short_description

  • description

  • component_ref – References a component to be found in an external library. The four attributes define the VLNV of the referenced element.

  • power_domain_links

  • vendor_extensions

  • id

Parameters:
component_ref: ConfigurableLibraryRefType | None
description: Description | None
display_name: DisplayName | None
id: str | None
instance_name: InstanceName | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.ComponentInstances(component_instance=<factory>)

Bases: object

Sub instances of internal components.

Parameters:

component_instance (Iterable[ComponentInstance])

component_instance: Iterable[ComponentInstance]
class org.accellera.ipxact.v1685_2022.ComponentInstantiationType(name=None, display_name=None, short_description=None, description=None, is_virtual=None, language=None, library_name=None, package_name=None, module_name=None, architecture_name=None, configuration_name=None, module_parameters=None, default_file_builder=<factory>, file_set_ref=<factory>, constraint_set_ref=<factory>, clearbox_element_refs=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Component instantiation type.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • is_virtual – When true, indicates that this component should not be netlisted.

  • language – The hardware description language used such as “verilog” or “vhdl”. If the attribute “strict” is “true”, this value must match the language being generated for the design.

  • library_name – A string specifying the library name in which the model should be compiled. If the libraryName element is not present then its value defaults to “work”.

  • package_name – A string describing the VHDL package containing the interface of the model. If the packageName element is not present then its value defaults to the component VLNV name concatenated with postfix “_cmp_pkg” which stands for component package.

  • module_name – A string describing the Verilog, SystemVerilog, or SystemC module name or the VHDL entity name. If the moduleName is not present then its value defaults to the component VLNV name

  • architecture_name – A string describing the VHDL architecture name. If the architectureName element is not present then its value defaults to “rtl”.

  • configuration_name – A string describing the Verilog, SystemVerilog, or VHDL configuration name. If the configurationName element is not present then its value defaults to the design configuration VLNV name of the design configuration associated with the active hierarchical view or, if there is no active hierarchical view, to the component VLNV name concatenated with postfix “_rtl_cfg”.

  • module_parameters – Model parameter name value pairs container

  • default_file_builder – Default command and flags used to build derived files from the sourceName files in the referenced file sets.

  • file_set_ref

  • constraint_set_ref

  • clearbox_element_refs – Container for clear box element references.

  • parameters

  • vendor_extensions

  • id

Parameters:
class ClearboxElementRefs(clearbox_element_ref=<factory>)

Bases: object

Variables:

clearbox_element_ref – Reference to a clear box element which is visible within this view.

Parameters:

clearbox_element_ref (Iterable[ClearboxElementRefType])

clearbox_element_ref: Iterable[ClearboxElementRefType]
class ModuleParameters(module_parameter=<factory>)

Bases: object

Variables:

module_parameter – A module parameter name value pair. The name is given in an attribute. The value is the element value. The dataType (applicable to high level modeling) is given in the dataType attribute. For hardware based models, the name should be identical to the RTL (VHDL generic or Verilog parameter). The usageType attribute indicates how the model parameter is to be used.

Parameters:

module_parameter (Iterable[ModuleParameterType])

module_parameter: Iterable[ModuleParameterType]
architecture_name: str | None
clearbox_element_refs: ClearboxElementRefs | None
configuration_name: str | None
constraint_set_ref: Iterable[ConstraintSetRef]
default_file_builder: Iterable[FileBuilderType]
description: Description | None
display_name: DisplayName | None
file_set_ref: Iterable[FileSetRef]
id: str | None
is_virtual: bool | None
language: LanguageType | None
library_name: str | None
module_name: str | None
module_parameters: ModuleParameters | None
name: str | None
package_name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.ComponentPortDirectionType(*values)

Bases: Enum

The direction of a component port.

IN = 'in'
INOUT = 'inout'
OUT = 'out'
PHANTOM = 'phantom'
class org.accellera.ipxact.v1685_2022.ComponentType(vendor=None, library=None, name=None, version=None, display_name=None, short_description=None, description=None, type_definitions=None, power_domains=None, bus_interfaces=None, indirect_interfaces=None, channels=None, modes=None, address_spaces=None, memory_maps=None, model=None, component_generators=None, choices=None, file_sets=None, clearbox_elements=None, cpus=None, other_clock_drivers=None, reset_types=None, parameters=None, assertions=None, vendor_extensions=None, id=None)

Bases: object

Component-specific extension to componentType.

Variables:

  • vendor – Name of the vendor who supplies this file.

  • library – Name of the logical library this element belongs to.

  • name – The name of the object.

  • version – Indicates the version of the named element.

  • display_name – Name for display purposes. Typically a few words providing a more detailed and/or user-friendly name than the vlnv.

  • short_description

  • description

  • type_definitions

  • power_domains

  • bus_interfaces

  • indirect_interfaces

  • channels

  • modes – A list of user defined component modes.

  • address_spaces

  • memory_maps

  • model

  • component_generators – Generator list is tools-specific.

  • choices

  • file_sets

  • clearbox_elements – A list of clearboxElements

  • cpus – cpu’s in the component

  • other_clock_drivers – Defines a set of clock drivers that are not directly associated with an input port of the component.

  • reset_types – A list of user defined resetTypes applicable to this component.

  • parameters

  • assertions

  • vendor_extensions

  • id

Parameters:
class ClearboxElements(clearbox_element=<factory>)

Bases: object

Variables:

clearbox_element – A clearboxElement is a useful way to identify elements of a component that can not be identified through other means such as internal signals and non- software accessible registers.

Parameters:

clearbox_element (Iterable[ClearboxElementType])

clearbox_element: Iterable[ClearboxElementType]
class Cpus(cpu=<factory>)

Bases: object

Variables:

cpu – Describes a processor in this component.

Parameters:

cpu (Iterable[Cpu])

class Cpu(name=None, display_name=None, short_description=None, description=None, range=None, width=None, regions=None, address_unit_bits=None, executable_image=<factory>, memory_map_ref=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • range – The address range of an address block. Expressed as the number of addressable units accessible to the block. The range and the width are related by the following formulas: number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range number_of_rows_in_block = number_of_bits_in_block / ipxact:width

  • width – The bit width of a row in the address block. The range and the width are related by the following formulas: number_of_bits_in_block = ipxact:addressUnitBits * ipxact:range number_of_rows_in_block = number_of_bits_in_block / ipxact:width

  • regions – Address regions within a cpu system address map.

  • address_unit_bits

  • executable_image

  • memory_map_ref – Indicates which memory maps into this cpu.

  • parameters – Data specific to the cpu.

  • vendor_extensions

  • id

Parameters:
class Regions(region=<factory>)

Bases: object

Variables:

region – Address region within a system address map.

Parameters:

region (Iterable[Region])

class Region(name=None, display_name=None, short_description=None, description=None, address_offset=None, range=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • address_offset – Address offset of the region within the system address map.

  • range – The address range of region. Expressed as the number of addressable units accessible to the region.

  • vendor_extensions

  • id

Parameters:
address_offset: UnsignedLongintExpression | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
range: UnsignedPositiveLongintExpression | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
region: Iterable[Region]
address_unit_bits: AddressUnitBits | None
description: Description | None
display_name: DisplayName | None
executable_image: Iterable[ExecutableImage]
id: str | None
memory_map_ref: str | None
name: str | None
parameters: Parameters | None
range: UnsignedPositiveLongintExpression | None
regions: Regions | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
width: UnsignedPositiveIntExpression | None
cpu: Iterable[Cpu]
class Modes(mode: collections.abc.Iterable['ComponentType.Modes.Mode'] = <factory>)

Bases: object

Parameters:

mode (Iterable[Mode])

class Mode(name=None, display_name=None, short_description=None, description=None, port_slice=<factory>, field_slice=<factory>, condition=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • port_slice

  • field_slice – Reference to a register field slice

  • condition

  • vendor_extensions

  • id

Parameters:
class FieldSlice(name=None, display_name=None, short_description=None, description=None, address_space_ref=None, memory_map_ref=None, memory_remap_ref=None, bank_ref=<factory>, address_block_ref=None, register_file_ref=<factory>, register_ref=None, alternate_register_ref=None, field_ref=None, range=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • address_space_ref

  • memory_map_ref

  • memory_remap_ref

  • bank_ref

  • address_block_ref

  • register_file_ref

  • register_ref

  • alternate_register_ref

  • field_ref

  • range

  • id

Parameters:
class AddressSpaceRef(address_space_ref: str | None = None)

Bases: object

Parameters:

address_space_ref (str | None)

address_space_ref: str | None
class MemoryMapRef(memory_map_ref: str | None = None)

Bases: object

Parameters:

memory_map_ref (str | None)

memory_map_ref: str | None
address_block_ref: AddressBlockRef | None
address_space_ref: AddressSpaceRef | None
alternate_register_ref: AlternateRegisterRef | None
bank_ref: Iterable[BankRef]
description: Description | None
display_name: DisplayName | None
field_ref: FieldRef | None
id: str | None
memory_map_ref: MemoryMapRef | None
memory_remap_ref: MemoryRemapRef | None
name: str | None
range: Range | None
register_file_ref: Iterable[RegisterFileRef]
register_ref: RegisterRef | None
short_description: ShortDescription | None
class PortSlice(name=None, display_name=None, short_description=None, description=None, port_ref=None, sub_port_reference=<factory>, part_select=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • port_ref

  • sub_port_reference

  • part_select

  • id

Parameters:
class PortRef(port_ref: str | None = None)

Bases: object

Parameters:

port_ref (str | None)

port_ref: str | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
part_select: PartSelect | None
port_ref: PortRef | None
short_description: ShortDescription | None
sub_port_reference: Iterable[SubPortReference]
condition: UnresolvedUnsignedBitExpression | None
description: Description | None
display_name: DisplayName | None
field_slice: Iterable[FieldSlice]
id: str | None
name: str | None
port_slice: Iterable[PortSlice]
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
mode: Iterable[Mode]
class PowerDomains(power_domain: collections.abc.Iterable['ComponentType.PowerDomains.PowerDomain'] = <factory>)

Bases: object

Parameters:

power_domain (Iterable[PowerDomain])

class PowerDomain(name=None, display_name=None, short_description=None, description=None, always_on=None, sub_domain_of=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • always_on

  • sub_domain_of – Reference to a power domain defined on this component

  • parameters

  • vendor_extensions

  • id

Parameters:
always_on: AlwaysOn | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
sub_domain_of: str | None
vendor_extensions: VendorExtensions | None
power_domain: Iterable[PowerDomain]
class ResetTypes(reset_type=<factory>)

Bases: object

Variables:

reset_type – A user defined reset policy

Parameters:

reset_type (Iterable[ResetType])

class ResetType(name=None, display_name=None, short_description=None, description=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • vendor_extensions

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
reset_type: Iterable[ResetType]
class TypeDefinitions(external_type_definitions: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.external_type_definitions.ExternalTypeDefinitions] = <factory>)

Bases: object

Parameters:

external_type_definitions (Iterable[ExternalTypeDefinitions])

external_type_definitions: Iterable[ExternalTypeDefinitions]
address_spaces: AddressSpaces | None
assertions: Assertions | None
bus_interfaces: BusInterfaces | None
channels: Channels | None
choices: Choices | None
clearbox_elements: ClearboxElements | None
component_generators: ComponentGenerators | None
cpus: Cpus | None
description: Description | None
display_name: str | None
file_sets: FileSets | None
id: str | None
indirect_interfaces: IndirectInterfaces | None
library: str | None
memory_maps: MemoryMaps | None
model: Model | None
modes: Modes | None
name: str | None
other_clock_drivers: OtherClocks | None
parameters: Parameters | None
power_domains: PowerDomains | None
reset_types: ResetTypes | None
short_description: ShortDescription | None
type_definitions: TypeDefinitions | None
vendor: str | None
vendor_extensions: VendorExtensions | None
version: str | None
class org.accellera.ipxact.v1685_2022.ConfigurableArrays(array=<factory>)

Bases: object

Variables:

array – Specific left and right array bounds.

Parameters:

array (Iterable[Array])

class Array(left: org.accellera.ipxact.v1685_2022.left.Left | None = None, right: org.accellera.ipxact.v1685_2022.right.Right | None = None, id: str | None = None)

Bases: object

Parameters:

  • left (Left | None)

  • right (Right | None)

  • id (str | None)

id: str | None
left: Left | None
right: Right | None
array: Iterable[Array]
class org.accellera.ipxact.v1685_2022.ConfigurableElementValue(value='', other_attributes=<factory>, reference_id=None, id=None)

Bases: ComplexBaseExpression

Describes the content of a configurable element.

The required referenceId attribute refers to the ID attribute of the configurable element.

Variables:

  • reference_id – Refers to the ID attribute of the configurable element.

  • id

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • reference_id (str | None)

  • id (str | None)

id: str | None
other_attributes: Mapping[str, str]
reference_id: str | None
value: str
class org.accellera.ipxact.v1685_2022.ConfigurableElementValues(configurable_element_value=<factory>)

Bases: object

All configuration information for a contained component, generator, generator chain or abstractor instance.

Variables:

configurable_element_value – Describes the content of a configurable element. The required referenceId attribute refers to the ID attribute of the configurable element.

Parameters:

configurable_element_value (Iterable[ConfigurableElementValue])

configurable_element_value: Iterable[ConfigurableElementValue]
class org.accellera.ipxact.v1685_2022.ConfigurableLibraryRefType(configurable_element_values=None, vendor=None, library=None, name=None, version=None, id=None)

Bases: object

Base IP-XACT document reference type for configurable top-level objects.

Contains vendor, library, name and version attributes along with configurable element values.

Parameters:

  • configurable_element_values (ConfigurableElementValues | None)

  • vendor (str | None)

  • library (str | None)

  • name (str | None)

  • version (str | None)

  • id (str | None)

configurable_element_values: ConfigurableElementValues | None
id: str | None
library: str | None
name: str | None
vendor: str | None
version: str | None
class org.accellera.ipxact.v1685_2022.ConstraintSet(name=None, display_name=None, short_description=None, description=None, vector=None, drive_constraint=None, load_constraint=None, timing_constraint=<factory>, constraint_set_id='default', id=None)

Bases: object

Defines constraints that apply to a component port.

If multiple constraintSet elements are used, each must have a unique value for the constraintSetId attribute.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • vector – The optional element vector specify the bits of a vector for which the constraints apply. The vaules of left and right must be within the range of the port. If the vector is not specified then the constraints apply to all the bits of the port.

  • drive_constraint

  • load_constraint

  • timing_constraint

  • constraint_set_id – Indicates a name for this set of constraints. Constraints are tied to a view using this name in the constraintSetRef element.

  • id

Parameters:
class Vector(left=None, right=None)

Bases: object

Variables:

  • left – The optional elements left and right can be used to select a bit-slice of a vector.

  • right – The optional elements left and right can be used to select a bit-slice of a vector.

Parameters:
left: UnsignedIntExpression | None
right: UnsignedIntExpression | None
constraint_set_id: str
description: Description | None
display_name: DisplayName | None
drive_constraint: DriveConstraint | None
id: str | None
load_constraint: LoadConstraint | None
name: str | None
short_description: ShortDescription | None
timing_constraint: Iterable[TimingConstraint]
vector: Vector | None
class org.accellera.ipxact.v1685_2022.ConstraintSetRef(local_name=None, vendor_extensions=None, id=None)

Bases: object

A reference to a set of port constraints.

Parameters:

  • local_name (str | None)

  • vendor_extensions (VendorExtensions | None)

  • id (str | None)

id: str | None
local_name: str | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.ConstraintSets(constraint_set=<factory>)

Bases: object

List of constraintSet elements for a component port.

Parameters:

constraint_set (Iterable[ConstraintSet])

constraint_set: Iterable[ConstraintSet]
class org.accellera.ipxact.v1685_2022.DataTypeType(*values)

Bases: Enum

Enumerates C argument data types.

CHAR = 'char *'
DOUBLE = 'double'
FLOAT = 'float'
INT = 'int'
LONG = 'long'
UNSIGNED_INT = 'unsigned int'
UNSIGNED_LONG = 'unsigned long'
VOID = 'void *'
class org.accellera.ipxact.v1685_2022.DefaultValue(value='', other_attributes=<factory>)

Bases: QualifiedExpression

Default value for a wire port.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.DelayValueType(*values)

Bases: Enum

Indicates the type of delay value - minimum or maximum delay.

MAX = 'max'
MIN = 'min'
class org.accellera.ipxact.v1685_2022.DelayValueUnitType(*values)

Bases: Enum

Indicates legal units for delay values.

NS = 'ns'
PS = 'ps'
class org.accellera.ipxact.v1685_2022.Dependency(value='', id=None)

Bases: IpxactUri

Specifies a location on which files or fileSets may be dependent.

Typically, this would be a directory that would contain included files.

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
class org.accellera.ipxact.v1685_2022.Description(value='')

Bases: object

Full description string, typically for documentation.

Parameters:

value (str)

value: str
class org.accellera.ipxact.v1685_2022.Design(vendor=None, library=None, name=None, version=None, display_name=None, short_description=None, description=None, component_instances=None, interconnections=None, ad_hoc_connections=None, choices=None, parameters=None, assertions=None, vendor_extensions=None, id=None)

Bases: object

Root element for a platform design.

Variables:

  • vendor – Name of the vendor who supplies this file.

  • library – Name of the logical library this element belongs to.

  • name – The name of the object.

  • version – Indicates the version of the named element.

  • display_name – Name for display purposes. Typically a few words providing a more detailed and/or user-friendly name than the vlnv.

  • short_description

  • description

  • component_instances

  • interconnections

  • ad_hoc_connections

  • choices

  • parameters

  • assertions

  • vendor_extensions

  • id

Parameters:
ad_hoc_connections: AdHocConnections | None
assertions: Assertions | None
choices: Choices | None
component_instances: ComponentInstances | None
description: Description | None
display_name: str | None
id: str | None
interconnections: Interconnections | None
library: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
vendor: str | None
vendor_extensions: VendorExtensions | None
version: str | None
class org.accellera.ipxact.v1685_2022.DesignConfiguration(vendor=None, library=None, name=None, version=None, display_name=None, short_description=None, description=None, design_ref=None, generator_chain_configuration=<factory>, interconnection_configuration=<factory>, view_configuration=<factory>, choices=None, parameters=None, assertions=None, vendor_extensions=None, id=None)

Bases: object

Top level element for describing the current configuration of a design.

Does not describe instance parameterization

Variables:

  • vendor – Name of the vendor who supplies this file.

  • library – Name of the logical library this element belongs to.

  • name – The name of the object.

  • version – Indicates the version of the named element.

  • display_name – Name for display purposes. Typically a few words providing a more detailed and/or user-friendly name than the vlnv.

  • short_description

  • description

  • design_ref – The design to which this configuration applies

  • generator_chain_configuration – Contains the configurable information associated with a generatorChain and its generators. Note that configurable information for generators associated with components is stored in the design file.

  • interconnection_configuration – Contains the information about the abstractors required to cross between two interfaces at with different abstractionDefs.

  • view_configuration – Contains the active views for each instance in the design

  • choices

  • parameters

  • assertions

  • vendor_extensions

  • id

Parameters:
class InterconnectionConfiguration(interconnection_ref=None, abstractor_instances=<factory>, vendor_extensions=None, id=None)

Bases: object

Variables:

  • interconnection_ref – Reference to the interconnection name, monitor interconnection name or possibly a hierConnection interfaceName in a design file.

  • abstractor_instances – List of abstractor-instances for this interconnection. Multiple abstractor-instances elements may be present for a 1-to-many (broadcast) interconnection. In that case, the optional interfaceRef elements must reference non-overlapping interfaces from the ‘many’ side of the interconnection.

  • vendor_extensions

  • id

Parameters:
class AbstractorInstances(interface_ref=<factory>, abstractor_instance=<factory>, vendor_extensions=None, id=None)

Bases: object

Variables:

  • interface_ref – Defines the broadcast endpoint to which this chain of abstractors applies.

  • abstractor_instance – Element to hold a the abstractor reference, the configuration and viewName. If multiple elements are present then the order is the order in which the abstractors should be chained together.

  • vendor_extensions

  • id

Parameters:
class AbstractorInstance(instance_name=None, display_name=None, short_description=None, description=None, abstractor_ref=None, view_name=None, id=None)

Bases: object

Variables:

  • instance_name – Instance name for the abstractor

  • display_name

  • short_description

  • description

  • abstractor_ref – Abstractor reference

  • view_name – The name of the active view for this abstractor instance.

  • id

Parameters:
abstractor_ref: ConfigurableLibraryRefType | None
description: Description | None
display_name: DisplayName | None
id: str | None
instance_name: str | None
short_description: ShortDescription | None
view_name: str | None
class InterfaceRef(vendor_extensions=None, component_ref=None, bus_ref=None, id=None)

Bases: object

Variables:

  • vendor_extensions

  • component_ref – Reference to a component instance nane.

  • bus_ref – Reference to a component bus interface name.

  • id

Parameters:

  • vendor_extensions (VendorExtensions | None)

  • component_ref (str | None)

  • bus_ref (str | None)

  • id (str | None)

bus_ref: str | None
component_ref: str | None
id: str | None
vendor_extensions: VendorExtensions | None
abstractor_instance: Iterable[AbstractorInstance]
id: str | None
interface_ref: Iterable[InterfaceRef]
vendor_extensions: VendorExtensions | None
abstractor_instances: Iterable[AbstractorInstances]
id: str | None
interconnection_ref: str | None
vendor_extensions: VendorExtensions | None
class ViewConfiguration(instance_name=None, view=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • instance_name

  • view – The selected view for the instance.

  • vendor_extensions

  • id

Parameters:
class View(configurable_element_values=None, view_ref=None)

Bases: object

Variables:

  • configurable_element_values – Parameter values to set in the selected configuredView.

  • view_ref

Parameters:
configurable_element_values: ConfigurableElementValues | None
view_ref: str | None
id: str | None
instance_name: InstanceName | None
vendor_extensions: VendorExtensions | None
view: View | None
assertions: Assertions | None
choices: Choices | None
description: Description | None
design_ref: LibraryRefType | None
display_name: str | None
generator_chain_configuration: Iterable[ConfigurableLibraryRefType]
id: str | None
interconnection_configuration: Iterable[InterconnectionConfiguration]
library: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
vendor: str | None
vendor_extensions: VendorExtensions | None
version: str | None
view_configuration: Iterable[ViewConfiguration]
class org.accellera.ipxact.v1685_2022.DesignConfigurationInstantiationType(name=None, display_name=None, short_description=None, description=None, language=None, design_configuration_ref=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Design configuration instantiation type.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • language – The hardware description language used such as “verilog” or “vhdl”. If the attribute “strict” is “true”, this value must match the language being generated for the design.

  • design_configuration_ref – References an IP-XACT design configuration document (by VLNV) that provides a configuration for the component’s design.

  • parameters

  • vendor_extensions

  • id

Parameters:
description: Description | None
design_configuration_ref: ConfigurableLibraryRefType | None
display_name: DisplayName | None
id: str | None
language: LanguageType | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.DesignInstantiationType(name=None, display_name=None, short_description=None, description=None, design_ref=None, vendor_extensions=None, id=None)

Bases: object

Design instantiation type.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • design_ref – References an IP-XACT design document (by VLNV) that provides a design for the component.

  • vendor_extensions

  • id

Parameters:
description: Description | None
design_ref: ConfigurableLibraryRefType | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.Dim(value='', other_attributes=<factory>, minimum=None, maximum=None, id=None, index_var=None)

Bases: UnsignedPositiveLongintExpression

Dimensions a register array, the semantics for dim elements are the same as the C language standard for the layout of memory in multidimensional arrays.

Variables:

  • id

  • index_var – Name for the index to allow referring to it in names and prosa.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

  • id (str | None)

  • index_var (str | None)

id: str | None
index_var: str | None
maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.Direction(*values)

Bases: Enum

IN = 'in'
INOUT = 'inout'
OUT = 'out'
class org.accellera.ipxact.v1685_2022.DisplayName(value='')

Bases: object

Element name for display purposes.

Typically a few words providing a more detailed and/or user-friendly name than the ipxact:name.

Parameters:

value (str)

value: str
class org.accellera.ipxact.v1685_2022.DomainTypeDef(type_name=None, type_definition=<factory>, view_ref=<factory>, id=None)

Bases: object

Definition of a single domain type defintion that can relate to multiple views.

Variables:

  • type_name – The name of the domain.

  • type_definition – Where the definition of the type is contained.

  • view_ref – A reference to a view in the file for which this type applies.

  • id

Parameters:
class TypeDefinition(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
class TypeName(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
class ViewRef(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
id: str | None
type_definition: Iterable[TypeDefinition]
type_name: TypeName | None
view_ref: Iterable[ViewRef]
class org.accellera.ipxact.v1685_2022.DomainTypeDefs(domain_type_def=<factory>)

Bases: object

The group of domain type definitions.

Parameters:

domain_type_def (Iterable[DomainTypeDef])

domain_type_def: Iterable[DomainTypeDef]
class org.accellera.ipxact.v1685_2022.DriveConstraint(cell_specification=None)

Bases: object

Defines a constraint indicating how an input is to be driven.

The preferred methodology is to specify a library cell in technology independent fashion. The implemention tool should assume that the associated port is driven by the specified cell, or that the drive strength of the input port is indicated by the specified resistance value.

Parameters:

cell_specification (CellSpecification | None)

cell_specification: CellSpecification | None
class org.accellera.ipxact.v1685_2022.Driver(range=None, view_ref=<factory>, default_value=None, clock_driver=None, single_shot_driver=None, id=None)

Bases: DriverType

Wire port driver element.

Parameters:
class ViewRef(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
clock_driver: ClockDriver | None
default_value: DefaultValue | None
id: str | None
range: Range | None
single_shot_driver: SingleShotDriver | None
view_ref: Iterable['DriverType.ViewRef']
class org.accellera.ipxact.v1685_2022.DriverType(range=None, view_ref=<factory>, default_value=None, clock_driver=None, single_shot_driver=None, id=None)

Bases: object

Wire port driver type.

Variables:

  • range

  • view_ref – A reference to a view in the file for which this type applies.

  • default_value

  • clock_driver

  • single_shot_driver

  • id

Parameters:
class ViewRef(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
clock_driver: ClockDriver | None
default_value: DefaultValue | None
id: str | None
range: Range | None
single_shot_driver: SingleShotDriver | None
view_ref: Iterable[ViewRef]
class org.accellera.ipxact.v1685_2022.Drivers(driver=<factory>)

Bases: object

Container for wire port driver elements.

Variables:

driver – Wire port driver element. If no range is specified, default value applies to the entire range.

Parameters:

driver (Iterable[Driver])

driver: Iterable[Driver]
class org.accellera.ipxact.v1685_2022.EdgeValueType(*values)

Bases: Enum

Indicates legal values for edge specification attributes.

FALL = 'fall'
RISE = 'rise'
class org.accellera.ipxact.v1685_2022.EndianessType(*values)

Bases: Enum

‘big’: means the most significant element of any multi-element data field is stored at the lowest memory address.

‘little’ means the least significant element of any multi-element data field is stored at the lowest memory address. If this element is not present the default is ‘little’ endian.

BIG = 'big'
LITTLE = 'little'
class org.accellera.ipxact.v1685_2022.EnumeratedValueType(name=None, display_name=None, short_description=None, description=None, value=None, vendor_extensions=None, usage=EnumeratedValueTypeUsage.READ_WRITE, id=None)

Bases: object

Enumerates specific values that can be assigned to the bit field.

The name of this enumerated value. This may be used as a token in generating code.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • value – Enumerated bit field value.

  • vendor_extensions

  • usage – Usage for the enumeration. ‘read’ for a software read access. ‘write’ for a software write access. ‘read-write’ for a software read or write access.

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
usage: EnumeratedValueTypeUsage
value: UnsignedBitVectorExpression | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.EnumeratedValueTypeUsage(*values)

Bases: Enum

READ = 'read'
READ_WRITE = 'read-write'
WRITE = 'write'
class org.accellera.ipxact.v1685_2022.EnumeratedValues(enumeration_definition_ref=None, enumerated_value=<factory>)

Bases: object

Enumerates specific values that can be assigned to the bit field.

Variables:

  • enumeration_definition_ref – References an enumeration to be found in a local or external library. The four attributes define the VLNV of the referenced element.

  • enumerated_value – Enumerates specific values that can be assigned to the bit field. The name of this enumerated value. This may be used as a token in generating code.

Parameters:
class EnumerationDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
enumerated_value: Iterable[EnumeratedValueType]
enumeration_definition_ref: EnumerationDefinitionRef | None
class org.accellera.ipxact.v1685_2022.EnumerationDefinitions(enumeration_definition: collections.abc.Iterable['EnumerationDefinitions.EnumerationDefinition'] = <factory>)

Bases: object

Parameters:

enumeration_definition (Iterable[EnumerationDefinition])

class EnumerationDefinition(name=None, display_name=None, short_description=None, description=None, width=None, enumerated_value=<factory>, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • width – Definition width used to resolve the value.

  • enumerated_value – Enumerates specific values that can be assigned to the bit field. The name of this enumerated value. This may be used as a token in generating code.

  • vendor_extensions

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
enumerated_value: Iterable[EnumeratedValueType]
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
width: UnsignedPositiveIntExpression | None
enumeration_definition: Iterable[EnumerationDefinition]
class org.accellera.ipxact.v1685_2022.ExecutableImage(name=None, display_name=None, short_description=None, description=None, parameters=None, language_tools=None, file_set_ref_group=None, vendor_extensions=None, image_id=None, image_type=None, id=None)

Bases: object

Specifies an executable software image to be loaded into a processors address space.

The format of the image is not specified. It could, for example, be an ELF loadfile, or it could be raw binary or ascii hex data for loading directly into a memory model instance.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • parameters – Additional information about the load module, e.g. stack base addresses, table addresses, etc.

  • language_tools – Default commands and flags for software language tools needed to build the executable image.

  • file_set_ref_group – Contains a group of file set references that indicates the set of file sets complying with the tool set of the current executable image.

  • vendor_extensions

  • image_id – Unique ID for the executableImage, referenced in fileSet/function/fileRef

  • image_type – Open element to describe the type of image. The contents is model and/or generator specific.

  • id

Parameters:
class FileSetRefGroup(file_set_ref: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.file_set_ref.FileSetRef] = <factory>)

Bases: object

Parameters:

file_set_ref (Iterable[FileSetRef])

file_set_ref: Iterable[FileSetRef]
class LanguageTools(file_builder=<factory>, linker=None, linker_flags=None, linker_command_file=<factory>)

Bases: object

Variables:

  • file_builder – A generic placeholder for any file builder like compilers and assemblers. It contains the file types to which the command should be applied, and the flags to be used with that command.

  • linker

  • linker_flags

  • linker_command_file

Parameters:
class FileBuilder(file_type=None, command=None, flags=None, replace_default_flags=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • file_type

  • command – Default command used to build files of the specified fileType.

  • flags – Flags given to the build command when building files of this type.

  • replace_default_flags – If true, replace any default flags value with the value in the sibling flags element. Otherwise, append the contents of the sibling flags element to any default flags value. If the value is true and the “flags” element is empty or missing, this will have the result of clearing any default flags value.

  • vendor_extensions

  • id

Parameters:
command: StringExpression | None
file_type: FileType | None
flags: StringExpression | None
id: str | None
replace_default_flags: UnsignedBitExpression | None
vendor_extensions: VendorExtensions | None
file_builder: Iterable[FileBuilder]
linker: StringExpression | None
linker_command_file: Iterable[LinkerCommandFile]
linker_flags: StringExpression | None
description: Description | None
display_name: DisplayName | None
file_set_ref_group: FileSetRefGroup | None
id: str | None
image_id: str | None
image_type: str | None
language_tools: LanguageTools | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.ExtendedVectorsType(vector=<factory>)

Bases: object

Variables:

vector – Left and right ranges of the vector.

Parameters:

vector (Iterable[Vector])

class Vector(left: org.accellera.ipxact.v1685_2022.left.Left | None = None, right: org.accellera.ipxact.v1685_2022.right.Right | None = None, vector_id: str | None = None, id: str | None = None)

Bases: object

Parameters:

  • left (Left | None)

  • right (Right | None)

  • vector_id (str | None)

  • id (str | None)

id: str | None
left: Left | None
right: Right | None
vector_id: str | None
vector: Iterable[Vector]
class org.accellera.ipxact.v1685_2022.ExternalPortReference(sub_port_reference=<factory>, part_select=None, vendor_extensions=None, port_ref=None, id=None)

Bases: object

Variables:

  • sub_port_reference

  • part_select

  • vendor_extensions

  • port_ref – A port on the on the referenced component from componentInterfaceRef.

  • id

Parameters:
id: str | None
part_select: PartSelect | None
port_ref: str | None
sub_port_reference: Iterable[SubPortReference]
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.ExternalTypeDefinitions(name=None, display_name=None, short_description=None, description=None, type_definitions_ref=None, view_links=None, mode_links=None, reset_type_links=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • type_definitions_ref – References a type definitions to be found in an external file. The four attributes define the VLNV of the referenced document.

  • view_links

  • mode_links

  • reset_type_links

  • vendor_extensions

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
type_definitions_ref: ConfigurableLibraryRefType | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.FieldAccessPolicyDefinitionRef(value='', type_definitions=None)

Bases: object

Indicates the accessibility of the data in the field.

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
class org.accellera.ipxact.v1685_2022.FieldAccessPolicyDefinitions(field_access_policy_definition: collections.abc.Iterable['FieldAccessPolicyDefinitions.FieldAccessPolicyDefinition'] = <factory>)

Bases: object

Parameters:

field_access_policy_definition (Iterable[FieldAccessPolicyDefinition])

class FieldAccessPolicyDefinition(name=None, display_name=None, short_description=None, description=None, access=None, modified_write_value=None, write_value_constraint=None, read_action=None, read_response=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access

  • modified_write_value

  • write_value_constraint

  • read_action

  • read_response

  • vendor_extensions

  • id

Parameters:
access: Access | None
description: Description | None
display_name: DisplayName | None
id: str | None
modified_write_value: ModifiedWriteValue | None
name: str | None
read_action: ReadAction | None
read_response: ReadResponse | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
write_value_constraint: WriteValueConstraint | None
field_access_policy_definition: Iterable[FieldAccessPolicyDefinition]
class org.accellera.ipxact.v1685_2022.FieldAccessPropertiesType(id: str | None = None)

Bases: object

Parameters:

id (str | None)

id: str | None
class org.accellera.ipxact.v1685_2022.FieldDefinitions(field_definition: collections.abc.Iterable['FieldDefinitions.FieldDefinition'] = <factory>)

Bases: object

Parameters:

field_definition (Iterable[FieldDefinition])

class FieldDefinition(name=None, display_name=None, short_description=None, description=None, type_identifier=None, bit_width=None, volatile=None, resets=None, field_access_policies=None, enumerated_values=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • type_identifier – Identifier name used to indicate that multiple field elements contain the exact same information for the elements in the fieldDefinitionGroup.

  • bit_width – Width of the field in bits.

  • volatile – Indicates whether the data is volatile. The presumed value is ‘false’ if not present.

  • resets

  • field_access_policies

  • enumerated_values

  • vendor_extensions

  • id

Parameters:
class FieldAccessPolicies(id: Optional[str] = None, field_access_policy: collections.abc.Iterable['FieldDefinitions.FieldDefinition.FieldAccessPolicies.FieldAccessPolicy'] = <factory>)

Bases: FieldAccessPropertiesType

Parameters:
class FieldAccessPolicy(mode_ref=<factory>, field_access_policy_definition_ref=None, access=None, modified_write_value=None, write_value_constraint=None, read_action=None, read_response=None, broadcasts=None, access_restrictions=None, testable=None, reserved=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • mode_ref

  • field_access_policy_definition_ref

  • access

  • modified_write_value

  • write_value_constraint

  • read_action

  • read_response

  • broadcasts

  • access_restrictions – Access restrictions

  • testable – Can the field be tested with an automated register test routine. The presumed value is true if not specified.

  • reserved – Indicates that the field should be documented as reserved. The presumed value is ‘0’ if not present.

  • vendor_extensions

  • id

Parameters:
class Broadcasts(broadcast_to: collections.abc.Iterable['FieldDefinitions.FieldDefinition.FieldAccessPolicies.FieldAccessPolicy.Broadcasts.BroadcastTo'] = <factory>)

Bases: object

Parameters:

broadcast_to (Iterable[BroadcastTo])

class BroadcastTo(address_space_ref: Optional[ForwardRef('FieldDefinitions.FieldDefinition.FieldAccessPolicies.FieldAccessPolicy.Broadcasts.BroadcastTo.AddressSpaceRef')] = None, memory_map_ref: Optional[ForwardRef('FieldDefinitions.FieldDefinition.FieldAccessPolicies.FieldAccessPolicy.Broadcasts.BroadcastTo.MemoryMapRef')] = None, memory_remap_ref: Optional[org.accellera.ipxact.v1685_2022.memory_remap_ref.MemoryRemapRef] = None, bank_ref: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.bank_ref.BankRef] = <factory>, address_block_ref: Optional[org.accellera.ipxact.v1685_2022.address_block_ref.AddressBlockRef] = None, register_file_ref: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.register_file_ref.RegisterFileRef] = <factory>, register_ref: Optional[org.accellera.ipxact.v1685_2022.register_ref.RegisterRef] = None, alternate_register_ref: Optional[org.accellera.ipxact.v1685_2022.alternate_register_ref.AlternateRegisterRef] = None, field_ref: Optional[org.accellera.ipxact.v1685_2022.field_ref.FieldRef] = None, id: Optional[str] = None)

Bases: object

Parameters:
class AddressSpaceRef(address_space_ref: str | None = None)

Bases: object

Parameters:

address_space_ref (str | None)

address_space_ref: str | None
class MemoryMapRef(memory_map_ref: str | None = None)

Bases: object

Parameters:

memory_map_ref (str | None)

memory_map_ref: str | None
address_block_ref: AddressBlockRef | None
address_space_ref: AddressSpaceRef | None
alternate_register_ref: AlternateRegisterRef | None
bank_ref: Iterable[BankRef]
field_ref: FieldRef | None
id: str | None
memory_map_ref: MemoryMapRef | None
memory_remap_ref: MemoryRemapRef | None
register_file_ref: Iterable[RegisterFileRef]
register_ref: RegisterRef | None
broadcast_to: Iterable[BroadcastTo]
class Testable(value=None, test_constraint=TestableTestConstraint.UNCONSTRAINED)

Bases: object

Variables:

  • value

  • test_constraint – Constraint for an automated register test routine. ‘unconstrained’ (default) means may read and write all legal values. ‘restore’ means may read and write legal values but the value must be restored to the initially read value before accessing another register. ‘writeAsRead’ has limitations on testability where only the value read before a write may be written to the field. ‘readOnly’ has limitations on testability where values may only be read from the field.

Parameters:
test_constraint: TestableTestConstraint
value: bool | None
access: Access | None
access_restrictions: AccessRestrictions | None
broadcasts: Broadcasts | None
field_access_policy_definition_ref: FieldAccessPolicyDefinitionRef | None
id: str | None
mode_ref: Iterable[ModeRef]
modified_write_value: ModifiedWriteValue | None
read_action: ReadAction | None
read_response: ReadResponse | None
reserved: UnsignedBitExpression | None
testable: Testable | None
vendor_extensions: VendorExtensions | None
write_value_constraint: WriteValueConstraint | None
field_access_policy: Iterable[FieldAccessPolicy]
id: str | None
class Resets(reset=<factory>)

Bases: object

Variables:

reset – BitField reset value

Parameters:

reset (Iterable[Reset])

reset: Iterable[Reset]
bit_width: UnsignedPositiveIntExpression | None
description: Description | None
display_name: DisplayName | None
enumerated_values: EnumeratedValues | None
field_access_policies: FieldAccessPolicies | None
id: str | None
name: str | None
resets: Resets | None
short_description: ShortDescription | None
type_identifier: str | None
vendor_extensions: VendorExtensions | None
volatile: bool | None
field_definition: Iterable[FieldDefinition]
class org.accellera.ipxact.v1685_2022.FieldMap(field_slice=None, sub_port_reference=<factory>, part_select=None, mode_ref=<factory>, id=None)

Bases: object

Maps slices of this port to component field slices.

Variables:

  • field_slice – Reference to a register field slice

  • sub_port_reference

  • part_select

  • mode_ref – A reference to a mode.

  • id

Parameters:
class FieldSlice(address_space_ref: Optional[ForwardRef('FieldMap.FieldSlice.AddressSpaceRef')] = None, memory_map_ref: Optional[ForwardRef('FieldMap.FieldSlice.MemoryMapRef')] = None, memory_remap_ref: Optional[org.accellera.ipxact.v1685_2022.memory_remap_ref.MemoryRemapRef] = None, bank_ref: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.bank_ref.BankRef] = <factory>, address_block_ref: Optional[org.accellera.ipxact.v1685_2022.address_block_ref.AddressBlockRef] = None, register_file_ref: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.register_file_ref.RegisterFileRef] = <factory>, register_ref: Optional[org.accellera.ipxact.v1685_2022.register_ref.RegisterRef] = None, alternate_register_ref: Optional[org.accellera.ipxact.v1685_2022.alternate_register_ref.AlternateRegisterRef] = None, field_ref: Optional[org.accellera.ipxact.v1685_2022.field_ref.FieldRef] = None, range: Optional[org.accellera.ipxact.v1685_2022.range.Range] = None)

Bases: object

Parameters:
class AddressSpaceRef(address_space_ref: str | None = None)

Bases: object

Parameters:

address_space_ref (str | None)

address_space_ref: str | None
class MemoryMapRef(memory_map_ref: str | None = None)

Bases: object

Parameters:

memory_map_ref (str | None)

memory_map_ref: str | None
address_block_ref: AddressBlockRef | None
address_space_ref: AddressSpaceRef | None
alternate_register_ref: AlternateRegisterRef | None
bank_ref: Iterable[BankRef]
field_ref: FieldRef | None
memory_map_ref: MemoryMapRef | None
memory_remap_ref: MemoryRemapRef | None
range: Range | None
register_file_ref: Iterable[RegisterFileRef]
register_ref: RegisterRef | None
class ModeRef(value: str = '', priority: int | None = None, id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • priority (int | None)

  • id (str | None)

id: str | None
priority: int | None
value: str
field_slice: FieldSlice | None
id: str | None
mode_ref: Iterable[ModeRef]
part_select: PartSelect | None
sub_port_reference: Iterable[SubPortReference]
class org.accellera.ipxact.v1685_2022.FieldMaps(field_map=<factory>)

Bases: object

Listing of maps between component port slices and field slices.

Parameters:

field_map (Iterable[FieldMap])

field_map: Iterable[FieldMap]
class org.accellera.ipxact.v1685_2022.FieldRef(indices: org.accellera.ipxact.v1685_2022.indices.Indices | None = None, field_ref: str | None = None)

Bases: object

Parameters:

  • indices (Indices | None)

  • field_ref (str | None)

field_ref: str | None
indices: Indices | None
class org.accellera.ipxact.v1685_2022.FieldType(name=None, display_name=None, short_description=None, description=None, access_handles=None, array=None, bit_offset=None, field_definition_ref=None, type_identifier=None, bit_width=None, volatile=None, resets=None, alias_of=None, field_access_policies=None, enumerated_values=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

A field within a register.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • array

  • bit_offset – Offset of this field’s bit 0 from bit 0 of the register.

  • field_definition_ref

  • type_identifier – Identifier name used to indicate that multiple field elements contain the exact same information for the elements in the fieldDefinitionGroup.

  • bit_width – Width of the field in bits.

  • volatile – Indicates whether the data is volatile. The presumed value is ‘false’ if not present.

  • resets

  • alias_of

  • field_access_policies

  • enumerated_values

  • parameters

  • vendor_extensions

  • id

Parameters:
class AliasOf(address_space_ref: Optional[ForwardRef('FieldType.AliasOf.AddressSpaceRef')] = None, memory_map_ref: Optional[ForwardRef('FieldType.AliasOf.MemoryMapRef')] = None, memory_remap_ref: Optional[org.accellera.ipxact.v1685_2022.memory_remap_ref.MemoryRemapRef] = None, bank_ref: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.bank_ref.BankRef] = <factory>, address_block_ref: Optional[org.accellera.ipxact.v1685_2022.address_block_ref.AddressBlockRef] = None, register_file_ref: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.register_file_ref.RegisterFileRef] = <factory>, register_ref: Optional[org.accellera.ipxact.v1685_2022.register_ref.RegisterRef] = None, alternate_register_ref: Optional[org.accellera.ipxact.v1685_2022.alternate_register_ref.AlternateRegisterRef] = None, field_ref: Optional[org.accellera.ipxact.v1685_2022.field_ref.FieldRef] = None)

Bases: object

Parameters:
class AddressSpaceRef(address_space_ref: str | None = None)

Bases: object

Parameters:

address_space_ref (str | None)

address_space_ref: str | None
class MemoryMapRef(memory_map_ref: str | None = None)

Bases: object

Parameters:

memory_map_ref (str | None)

memory_map_ref: str | None
address_block_ref: AddressBlockRef | None
address_space_ref: AddressSpaceRef | None
alternate_register_ref: AlternateRegisterRef | None
bank_ref: Iterable[BankRef]
field_ref: FieldRef | None
memory_map_ref: MemoryMapRef | None
memory_remap_ref: MemoryRemapRef | None
register_file_ref: Iterable[RegisterFileRef]
register_ref: RegisterRef | None
class Array(dim: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.dim.Dim] = <factory>, bit_stride: Optional[org.accellera.ipxact.v1685_2022.bit_stride.BitStride] = None)

Bases: object

Parameters:
bit_stride: BitStride | None
dim: Iterable[Dim]
class FieldAccessPolicies(id: Optional[str] = None, field_access_policy: collections.abc.Iterable['FieldType.FieldAccessPolicies.FieldAccessPolicy'] = <factory>)

Bases: FieldAccessPropertiesType

Parameters:
class FieldAccessPolicy(mode_ref=<factory>, field_access_policy_definition_ref=None, access=None, modified_write_value=None, write_value_constraint=None, read_action=None, read_response=None, broadcasts=None, access_restrictions=None, testable=None, reserved=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • mode_ref

  • field_access_policy_definition_ref

  • access

  • modified_write_value

  • write_value_constraint

  • read_action

  • read_response

  • broadcasts

  • access_restrictions – Access restrictions

  • testable – Can the field be tested with an automated register test routine. The presumed value is true if not specified.

  • reserved – Indicates that the field should be documented as reserved. The presumed value is ‘0’ if not present.

  • vendor_extensions

  • id

Parameters:
class Broadcasts(broadcast_to: collections.abc.Iterable['FieldType.FieldAccessPolicies.FieldAccessPolicy.Broadcasts.BroadcastTo'] = <factory>)

Bases: object

Parameters:

broadcast_to (Iterable[BroadcastTo])

class BroadcastTo(address_space_ref: Optional[ForwardRef('FieldType.FieldAccessPolicies.FieldAccessPolicy.Broadcasts.BroadcastTo.AddressSpaceRef')] = None, memory_map_ref: Optional[ForwardRef('FieldType.FieldAccessPolicies.FieldAccessPolicy.Broadcasts.BroadcastTo.MemoryMapRef')] = None, memory_remap_ref: Optional[org.accellera.ipxact.v1685_2022.memory_remap_ref.MemoryRemapRef] = None, bank_ref: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.bank_ref.BankRef] = <factory>, address_block_ref: Optional[org.accellera.ipxact.v1685_2022.address_block_ref.AddressBlockRef] = None, register_file_ref: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.register_file_ref.RegisterFileRef] = <factory>, register_ref: Optional[org.accellera.ipxact.v1685_2022.register_ref.RegisterRef] = None, alternate_register_ref: Optional[org.accellera.ipxact.v1685_2022.alternate_register_ref.AlternateRegisterRef] = None, field_ref: Optional[org.accellera.ipxact.v1685_2022.field_ref.FieldRef] = None, id: Optional[str] = None)

Bases: object

Parameters:
class AddressSpaceRef(address_space_ref: str | None = None)

Bases: object

Parameters:

address_space_ref (str | None)

address_space_ref: str | None
class MemoryMapRef(memory_map_ref: str | None = None)

Bases: object

Parameters:

memory_map_ref (str | None)

memory_map_ref: str | None
address_block_ref: AddressBlockRef | None
address_space_ref: AddressSpaceRef | None
alternate_register_ref: AlternateRegisterRef | None
bank_ref: Iterable[BankRef]
field_ref: FieldRef | None
id: str | None
memory_map_ref: MemoryMapRef | None
memory_remap_ref: MemoryRemapRef | None
register_file_ref: Iterable[RegisterFileRef]
register_ref: RegisterRef | None
broadcast_to: Iterable[BroadcastTo]
class Testable(value=None, test_constraint=TestableTestConstraint.UNCONSTRAINED)

Bases: object

Variables:

  • value

  • test_constraint – Constraint for an automated register test routine. ‘unconstrained’ (default) means may read and write all legal values. ‘restore’ means may read and write legal values but the value must be restored to the initially read value before accessing another register. ‘writeAsRead’ has limitations on testability where only the value read before a write may be written to the field. ‘readOnly’ has limitations on testability where values may only be read from the field.

Parameters:
test_constraint: TestableTestConstraint
value: bool | None
access: Access | None
access_restrictions: AccessRestrictions | None
broadcasts: Broadcasts | None
field_access_policy_definition_ref: FieldAccessPolicyDefinitionRef | None
id: str | None
mode_ref: Iterable[ModeRef]
modified_write_value: ModifiedWriteValue | None
read_action: ReadAction | None
read_response: ReadResponse | None
reserved: UnsignedBitExpression | None
testable: Testable | None
vendor_extensions: VendorExtensions | None
write_value_constraint: WriteValueConstraint | None
field_access_policy: Iterable[FieldAccessPolicy]
id: str | None
class FieldDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
class Resets(reset=<factory>)

Bases: object

Variables:

reset – BitField reset value

Parameters:

reset (Iterable[Reset])

reset: Iterable[Reset]
access_handles: AccessHandles | None
alias_of: AliasOf | None
array: Array | None
bit_offset: UnsignedIntExpression | None
bit_width: UnsignedPositiveIntExpression | None
description: Description | None
display_name: DisplayName | None
enumerated_values: EnumeratedValues | None
field_access_policies: FieldAccessPolicies | None
field_definition_ref: FieldDefinitionRef | None
id: str | None
name: str | None
parameters: Parameters | None
resets: Resets | None
short_description: ShortDescription | None
type_identifier: str | None
vendor_extensions: VendorExtensions | None
volatile: bool | None
class org.accellera.ipxact.v1685_2022.File(name=None, file_type=<factory>, is_structural=None, is_include_file=None, logical_name=None, exported_name=<factory>, build_command=None, dependency=<factory>, define=<factory>, image_type=<factory>, description=None, vendor_extensions=None, file_id=None, other_attributes=<factory>, id=None)

Bases: object

IP-XACT reference to a file or directory.

Variables:

  • name – Path to the file or directory. If this path is a relative path, then it is relative to the containing XML file.

  • file_type

  • is_structural – Indicates that the current file is purely structural.

  • is_include_file – Indicate that the file is include file.

  • logical_name – Logical name for this file or directory e.g. VHDL library name.

  • exported_name – Defines exported names that can be accessed externally, e.g. exported function names from a C source file.

  • build_command – Command and flags used to build derived files from the sourceName files. If this element is present, the command and/or flags used to to build the file will override or augment any default builders at a higher level.

  • dependency

  • define – Specifies define symbols that are used in the source file. The ipxact:name element gives the name to be defined and the text content of the ipxact:value element holds the value. This element supports full configurability.

  • image_type – Relates the current file to a certain executable image type in the design.

  • description – String for describing this file to users

  • vendor_extensions

  • file_id – Unique ID for this file, referenced in fileSet/function/fileRef

  • other_attributes

  • id

Parameters:
class BuildCommand(command=None, flags=None, replace_default_flags=None, target_name=None)

Bases: object

Variables:

  • command – Command used to build this file.

  • flags – Flags given to the build command when building this file. If the optional attribute “append” is “true”, this string will be appended to any existing flags, otherwise these flags will replace any existing default flags.

  • replace_default_flags – If true, the value of the sibling element “flags” should replace any default flags specified at a more global level. If this is true and the sibling element “flags” is empty or missing, this has the effect of clearing any default flags.

  • target_name – Pathname to the file that is derived (built) from the source file.

Parameters:
class Flags(value='', other_attributes=<factory>, append=None)

Bases: StringExpression

Variables:

append – “true” indicates that the flags shall be appended to any existing flags, “false”indicates these flags will replace any existing default flags.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • append (bool | None)

append: bool | None
other_attributes: Mapping[str, str]
value: str
command: StringExpression | None
flags: Flags | None
replace_default_flags: UnsignedBitExpression | None
target_name: IpxactUri | None
class ExportedName(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
class ImageType(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
class IsIncludeFile(value=None, external_declarations=False)

Bases: object

Variables:

  • value

  • external_declarations – the File contains some declarations that are needed in top file

Parameters:

  • value (bool | None)

  • external_declarations (bool)

external_declarations: bool
value: bool | None
class LogicalName(value='', default=False)

Bases: object

Variables:

  • value

  • default – The logical name shall only be used as a default and another process may override this name.

Parameters:

  • value (str)

  • default (bool)

default: bool
value: str
build_command: BuildCommand | None
define: Iterable[NameValuePairType]
dependency: Iterable[Dependency]
description: str | None
exported_name: Iterable[ExportedName]
file_id: str | None
file_type: Iterable[FileType]
id: str | None
image_type: Iterable[ImageType]
is_include_file: IsIncludeFile | None
is_structural: bool | None
logical_name: LogicalName | None
name: IpxactUri | None
other_attributes: Mapping[str, str]
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.FileBuilderType(file_type=None, command=None, flags=None, replace_default_flags=None, id=None)

Bases: object

Variables:

  • file_type

  • command – Default command used to build files of the specified fileType.

  • flags – Flags given to the build command when building files of this type.

  • replace_default_flags – If true, replace any default flags value with the value in the sibling flags element. Otherwise, append the contents of the sibling flags element to any default flags value. If the value is true and the “flags” element is empty or missing, this will have the result of clearing any default flags value.

  • id

Parameters:
command: StringExpression | None
file_type: FileType | None
flags: StringExpression | None
id: str | None
replace_default_flags: UnsignedBitExpression | None
class org.accellera.ipxact.v1685_2022.FileSet(name=None, display_name=None, short_description=None, description=None, group=<factory>, file=<factory>, default_file_builder=<factory>, dependency=<factory>, function=<factory>, vendor_extensions=None, id=None)

Bases: FileSetType

This element specifies a list of unique pathnames to files and directories.

It may also include build instructions for the files. If compilation order is important, e.g. for VHDL files, the files have to be provided in compilation order.

Parameters:
class Function(entry_point=None, file_ref=None, return_type=None, argument=<factory>, disabled=None, source_file=<factory>, replicate=False, id=None)

Bases: object

Variables:

  • entry_point – Optional name for the function.

  • file_ref – A reference to the file that contains the entry point function.

  • return_type – Function return type. Possible values are void and int.

  • argument – Arguments passed in when the function is called. Arguments are passed in order. This is an extension of the name-value pair which includes the data type in the ipxact:dataType attribute. The argument name is in the ipxact:name element and its value is in the ipxact:value element.

  • disabled – Specifies if the SW function is enabled. If not present the function is always enabled.

  • source_file – Location information for the source file of this function.

  • replicate – If true directs the generator to compile a separate object module for each instance of the component in the design. If false (default) the function will be called with different arguments for each instance.

  • id

Parameters:
class Argument(name=None, display_name=None, short_description=None, description=None, value=None, vendor_extensions=None, id=None, data_type=None)

Bases: NameValuePairType

Variables:

data_type – The data type of the argument as pertains to the language. Example: “int”, “double”, “char *”.

Parameters:
data_type: DataTypeType | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
value: Value | None
vendor_extensions: VendorExtensions | None
class SourceFile(source_name=None, file_type=None, id=None)

Bases: object

Variables:

  • source_name – Source file for the boot load. Relative names are searched for in the project directory and the source of the component directory.

  • file_type

  • id

Parameters:
file_type: FileType | None
id: str | None
source_name: IpxactUri | None
argument: Iterable[Argument]
disabled: UnsignedBitExpression | None
entry_point: str | None
file_ref: str | None
id: str | None
replicate: bool
return_type: ReturnTypeType | None
source_file: Iterable[SourceFile]
default_file_builder: Iterable[FileBuilderType]
dependency: Iterable[Dependency]
description: Description | None
display_name: DisplayName | None
file: Iterable[File]
function: Iterable['FileSetType.Function']
group: Iterable['FileSetType.Group']
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.FileSetRef(local_name=None, vendor_extensions=None, id=None)

Bases: object

A reference to a fileSet.

Variables:

  • local_name – Refers to a fileSet defined within this description.

  • vendor_extensions

  • id

Parameters:

  • local_name (str | None)

  • vendor_extensions (VendorExtensions | None)

  • id (str | None)

id: str | None
local_name: str | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.FileSetType(name=None, display_name=None, short_description=None, description=None, group=<factory>, file=<factory>, default_file_builder=<factory>, dependency=<factory>, function=<factory>, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • group – Identifies this filleSet as belonging to a particular group or having a particular purpose. Examples might be “diagnostics”, “boot”, “application”, “interrupt”, “deviceDriver”, etc.

  • file

  • default_file_builder – Default command and flags used to build derived files from the sourceName files in this file set.

  • dependency

  • function – Generator information if this file set describes a function. For example, this file set may describe diagnostics for which the DE can generate a diagnostics driver.

  • vendor_extensions

  • id

Parameters:
class Function(entry_point=None, file_ref=None, return_type=None, argument=<factory>, disabled=None, source_file=<factory>, replicate=False, id=None)

Bases: object

Variables:

  • entry_point – Optional name for the function.

  • file_ref – A reference to the file that contains the entry point function.

  • return_type – Function return type. Possible values are void and int.

  • argument – Arguments passed in when the function is called. Arguments are passed in order. This is an extension of the name-value pair which includes the data type in the ipxact:dataType attribute. The argument name is in the ipxact:name element and its value is in the ipxact:value element.

  • disabled – Specifies if the SW function is enabled. If not present the function is always enabled.

  • source_file – Location information for the source file of this function.

  • replicate – If true directs the generator to compile a separate object module for each instance of the component in the design. If false (default) the function will be called with different arguments for each instance.

  • id

Parameters:
class Argument(name=None, display_name=None, short_description=None, description=None, value=None, vendor_extensions=None, id=None, data_type=None)

Bases: NameValuePairType

Variables:

data_type – The data type of the argument as pertains to the language. Example: “int”, “double”, “char *”.

Parameters:
data_type: DataTypeType | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
value: Value | None
vendor_extensions: VendorExtensions | None
class SourceFile(source_name=None, file_type=None, id=None)

Bases: object

Variables:

  • source_name – Source file for the boot load. Relative names are searched for in the project directory and the source of the component directory.

  • file_type

  • id

Parameters:
file_type: FileType | None
id: str | None
source_name: IpxactUri | None
argument: Iterable[Argument]
disabled: UnsignedBitExpression | None
entry_point: str | None
file_ref: str | None
id: str | None
replicate: bool
return_type: ReturnTypeType | None
source_file: Iterable[SourceFile]
default_file_builder: Iterable[FileBuilderType]
dependency: Iterable[Dependency]
description: Description | None
display_name: DisplayName | None
file: Iterable[File]
function: Iterable[Function]
group: Iterable[Group]
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.FileSets(file_set=<factory>)

Bases: object

List of file sets associated with component.

Parameters:

file_set (Iterable[FileSet])

file_set: Iterable[FileSet]
class org.accellera.ipxact.v1685_2022.FileType(value=None, user=None, libext=None, id=None)

Bases: object

Enumerated file types known by IP-XACT.

Parameters:

  • value (SimpleFileType | None)

  • user (str | None)

  • libext (str | None)

  • id (str | None)

id: str | None
libext: str | None
user: str | None
value: SimpleFileType | None
class org.accellera.ipxact.v1685_2022.FormatType(*values)

Bases: Enum

This is an indication on the format of the value.

bit: 1-bit or more (vector) bits unsigned integer, byte: 8-bit signed integer, shortint: 16-bit signed integer, int: 32-bit signed integer, longint: 64-bit signed integer, shortreal: 32-bit signed floating point number, real: 64-bit signed floating point number, string: textual information.

BIT = 'bit'
BYTE = 'byte'
INT = 'int'
LONGINT = 'longint'
REAL = 'real'
SHORTINT = 'shortint'
SHORTREAL = 'shortreal'
STRING = 'string'
class org.accellera.ipxact.v1685_2022.Generator(name=None, display_name=None, short_description=None, description=None, phase=None, parameters=None, api_type=None, api_service=None, transport_methods=None, generator_exe=None, vendor_extensions=None, hidden=False, id=None)

Bases: GeneratorType

Specifies a set of generators.

Parameters:
api_service: GeneratorTypeApiService | None
api_type: 'GeneratorType.ApiType' | None
description: Description | None
display_name: DisplayName | None
generator_exe: IpxactUri | None
hidden: bool
id: str | None
name: str | None
parameters: Parameters | None
phase: Phase | None
short_description: ShortDescription | None
transport_methods: 'GeneratorType.TransportMethods' | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.GeneratorChain(vendor=None, library=None, name=None, version=None, display_name=None, short_description=None, description=None, generator_chain_selector=<factory>, component_generator_selector=<factory>, generator=<factory>, chain_group=<factory>, choices=None, parameters=None, assertions=None, vendor_extensions=None, hidden=False, id=None)

Bases: object

Variables:

  • vendor – Name of the vendor who supplies this file.

  • library – Name of the logical library this element belongs to.

  • name – The name of the object.

  • version – Indicates the version of the named element.

  • display_name – Name for display purposes. Typically a few words providing a more detailed and/or user-friendly name than the vlnv.

  • short_description

  • description

  • generator_chain_selector – Select other generator chain files for inclusion into this chain. The boolean attribute “unique” (default false) specifies that only a single generator is valid in this context. If more that one generator is selected based on the selection criteria, DE will prompt the user to resolve to a single generator.

  • component_generator_selector – Selects generators declared in components of the current design for inclusion into this generator chain.

  • generator

  • chain_group – Identifies this generator chain as belonging to the named group. This is used by other generator chains to select this chain for programmatic inclusion.

  • choices

  • parameters

  • assertions

  • vendor_extensions

  • hidden – If this attribute is true then the generator should not be presented to the user, it may be part of a chain and has no useful meaning when invoked standalone.

  • id

Parameters:
class ChainGroup(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
class GeneratorChainSelector(group_selector=None, generator_chain_ref=None, unique=False, id=None)

Bases: object

Variables:

  • group_selector

  • generator_chain_ref – Select another generator chain using the unique identifier of this generator chain.

  • unique – Specifies that only a single generator is valid in this context. If more that one generator is selcted based on the selection criteria, DE will prompt the user to resolve to a single generator.

  • id

Parameters:
generator_chain_ref: ConfigurableLibraryRefType | None
group_selector: GroupSelector | None
id: str | None
unique: bool
assertions: Assertions | None
chain_group: Iterable[ChainGroup]
choices: Choices | None
component_generator_selector: Iterable[GeneratorSelectorType]
description: Description | None
display_name: str | None
generator: Iterable[Generator]
generator_chain_selector: Iterable[GeneratorChainSelector]
hidden: bool
id: str | None
library: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
vendor: str | None
vendor_extensions: VendorExtensions | None
version: str | None
class org.accellera.ipxact.v1685_2022.GeneratorRef(value='', id=None)

Bases: object

A reference to a generator element.

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
class org.accellera.ipxact.v1685_2022.GeneratorSelectorType(group_selector: org.accellera.ipxact.v1685_2022.group_selector.GroupSelector | None = None, id: str | None = None)

Bases: object

Parameters:
group_selector: GroupSelector | None
id: str | None
class org.accellera.ipxact.v1685_2022.GeneratorType(name=None, display_name=None, short_description=None, description=None, phase=None, parameters=None, api_type=None, api_service=None, transport_methods=None, generator_exe=None, vendor_extensions=None, hidden=False, id=None)

Bases: object

Types of generators.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • phase

  • parameters

  • api_type – Indicates the type of API used by the generator. Valid value are TGI_2009, TGI_2014_BASE, TGI_2014_EXTENDED, TGI_2022_BASE, TGI_2022_EXTENDED, and none. If this element is not present, TGI_2022_BASE is assumed. The type TGI_2009 indicates a generator using the 1685-2009 version of the TGI API. The types TGI_2014_BASE and TGI_2014_EXTENDED indicate a generator using the 1685-2014 version of the TGI API. Types TGI_2009, TGI_2014_BASE, and TGI_2014_EXTENDED are not part of the 1685-2022 version of the standard and may not be supported by Design Environments

  • api_service – Communication Mechanism. Can be one of SOAP or REST (defaults to SOAP)

  • transport_methods

  • generator_exe – The pathname to the executable file that implements the generator

  • vendor_extensions

  • hidden – If this attribute is true then the generator should not be presented to the user, it may be part of a chain and has no useful meaning when invoked standalone.

  • id

Parameters:
api_service: GeneratorTypeApiService | None
api_type: ApiType | None
description: Description | None
display_name: DisplayName | None
generator_exe: IpxactUri | None
hidden: bool
id: str | None
name: str | None
parameters: Parameters | None
phase: Phase | None
short_description: ShortDescription | None
transport_methods: TransportMethods | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.GeneratorTypeApiService(*values)

Bases: Enum

REST = 'REST'
SOAP = 'SOAP'
class org.accellera.ipxact.v1685_2022.GroupSelector(name=<factory>, multiple_group_selection_operator=GroupSelectorMultipleGroupSelectionOperator.OR, id=None)

Bases: object

Specifies a set of group names used to select subsequent generators.

The attribute “multipleGroupOperator” specifies the OR or AND selection operator if there is more than one group name (default=OR).

Variables:

  • name – Specifies a generator group name or a generator chain group name to be selected for inclusion in the generator chain.

  • multiple_group_selection_operator – Specifies the OR or AND selection operator if there is more than one group name.

  • id

Parameters:
class Name(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
id: str | None
multiple_group_selection_operator: GroupSelectorMultipleGroupSelectionOperator
name: Iterable[Name]
class org.accellera.ipxact.v1685_2022.GroupSelectorMultipleGroupSelectionOperator(*values)

Bases: Enum

AND = 'and'
OR = 'or'
class org.accellera.ipxact.v1685_2022.HierInterfaceType(description=None, vendor_extensions=None, bus_ref=None, id=None)

Bases: object

A representation of an exported interface.

The busRef indicates the name of the interface in the containing component.

Variables:

  • description

  • vendor_extensions

  • bus_ref – Reference to the components bus interface

  • id

Parameters:
bus_ref: str | None
description: Description | None
id: str | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.Index(value='', other_attributes=<factory>, minimum=None, maximum=None, id=None)

Bases: UnsignedIntExpression

An index into an object in the referenced view.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

  • id (str | None)

id: str | None
maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.Indices(index: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.index.Index] = <factory>)

Bases: IndicesType

Parameters:

index (Iterable[Index])

index: Iterable[Index]
class org.accellera.ipxact.v1685_2022.IndicesType(index: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.index.Index] = <factory>)

Bases: object

Parameters:

index (Iterable[Index])

index: Iterable[Index]
class org.accellera.ipxact.v1685_2022.IndirectAddressRef(address_space_ref=None, memory_map_ref=None, memory_remap_ref=None, bank_ref=<factory>, address_block_ref=None, register_file_ref=<factory>, register_ref=None, alternate_register_ref=None, field_ref=None)

Bases: object

A reference to a field used for addressing the indirectly accessible memoryMap.

Parameters:
class AddressSpaceRef(address_space_ref: str | None = None)

Bases: object

Parameters:

address_space_ref (str | None)

address_space_ref: str | None
class MemoryMapRef(memory_map_ref: str | None = None)

Bases: object

Parameters:

memory_map_ref (str | None)

memory_map_ref: str | None
address_block_ref: AddressBlockRef | None
address_space_ref: AddressSpaceRef | None
alternate_register_ref: AlternateRegisterRef | None
bank_ref: Iterable[BankRef]
field_ref: FieldRef | None
memory_map_ref: MemoryMapRef | None
memory_remap_ref: MemoryRemapRef | None
register_file_ref: Iterable[RegisterFileRef]
register_ref: RegisterRef | None
class org.accellera.ipxact.v1685_2022.IndirectDataRef(address_space_ref=None, memory_map_ref=None, memory_remap_ref=None, bank_ref=<factory>, address_block_ref=None, register_file_ref=<factory>, register_ref=None, alternate_register_ref=None, field_ref=None)

Bases: object

A reference to a field used for read/write access to the indirectly accessible memoryMap.

Parameters:
class AddressSpaceRef(address_space_ref: str | None = None)

Bases: object

Parameters:

address_space_ref (str | None)

address_space_ref: str | None
class MemoryMapRef(memory_map_ref: str | None = None)

Bases: object

Parameters:

memory_map_ref (str | None)

memory_map_ref: str | None
address_block_ref: AddressBlockRef | None
address_space_ref: AddressSpaceRef | None
alternate_register_ref: AlternateRegisterRef | None
bank_ref: Iterable[BankRef]
field_ref: FieldRef | None
memory_map_ref: MemoryMapRef | None
memory_remap_ref: MemoryRemapRef | None
register_file_ref: Iterable[RegisterFileRef]
register_ref: RegisterRef | None
class org.accellera.ipxact.v1685_2022.IndirectInterface(name=None, display_name=None, short_description=None, description=None, indirect_address_ref=None, indirect_data_ref=None, memory_map_ref=None, transparent_bridge=<factory>, bits_in_lau=None, endianness=None, parameters=None, vendor_extensions=None, id=None, any_attributes=<factory>)

Bases: IndirectInterfaceType

Describes one of the bus interfaces supported by this component.

Parameters:
any_attributes: Mapping[str, str]
bits_in_lau: BitsInLau | None
description: Description | None
display_name: DisplayName | None
endianness: EndianessType | None
id: str | None
indirect_address_ref: IndirectAddressRef | None
indirect_data_ref: IndirectDataRef | None
memory_map_ref: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
transparent_bridge: Iterable[TransparentBridge]
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.IndirectInterfaceType(name=None, display_name=None, short_description=None, description=None, indirect_address_ref=None, indirect_data_ref=None, memory_map_ref=None, transparent_bridge=<factory>, bits_in_lau=None, endianness=None, parameters=None, vendor_extensions=None, id=None, any_attributes=<factory>)

Bases: object

Type definition for a indirectInterface in a component.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • indirect_address_ref

  • indirect_data_ref

  • memory_map_ref – A reference to a memoryMap. This memoryMap is indirectly accessible through this interface.

  • transparent_bridge

  • bits_in_lau

  • endianness – ‘big’: means the most significant element of any multi-element data field is stored at the lowest memory address. ‘little’ means the least significant element of any multi-element data field is stored at the lowest memory address. If this element is not present the default is ‘little’ endian.

  • parameters

  • vendor_extensions

  • id

  • any_attributes

Parameters:
any_attributes: Mapping[str, str]
bits_in_lau: BitsInLau | None
description: Description | None
display_name: DisplayName | None
endianness: EndianessType | None
id: str | None
indirect_address_ref: IndirectAddressRef | None
indirect_data_ref: IndirectDataRef | None
memory_map_ref: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
transparent_bridge: Iterable[TransparentBridge]
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.IndirectInterfaces(indirect_interface=<factory>)

Bases: object

A list of bus interfaces supported by this component.

Parameters:

indirect_interface (Iterable[IndirectInterface])

indirect_interface: Iterable[IndirectInterface]
class org.accellera.ipxact.v1685_2022.Initiative(value=None)

Bases: object

If this element is present, the type of access is restricted to the specified value.

Parameters:

value (InitiativeType | None)

value: InitiativeType | None
class org.accellera.ipxact.v1685_2022.InitiativeType(*values)

Bases: Enum

BOTH = 'both'
PHANTOM = 'phantom'
PROVIDES = 'provides'
REQUIRES = 'requires'
class org.accellera.ipxact.v1685_2022.InstanceGeneratorType(name=None, display_name=None, short_description=None, description=None, phase=None, parameters=None, api_type=None, api_service=None, transport_methods=None, generator_exe=None, vendor_extensions=None, hidden=False, id=None, group=<factory>, scope=InstanceGeneratorTypeScope.INSTANCE)

Bases: GeneratorType

Variables:

  • group – An identifier to specify the generator group. This is used by generator chains for selecting which generators to run.

  • scope – The scope attribute applies to component generators and specifies whether the generator should be run for each instance of the entity (or module) or just once for all instances of the entity.

Parameters:
api_service: GeneratorTypeApiService | None
api_type: 'GeneratorType.ApiType' | None
description: Description | None
display_name: DisplayName | None
generator_exe: IpxactUri | None
group: Iterable[InstanceGeneratorType.Group]
hidden: bool
id: str | None
name: str | None
parameters: Parameters | None
phase: Phase | None
scope: InstanceGeneratorTypeScope
short_description: ShortDescription | None
transport_methods: 'GeneratorType.TransportMethods' | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.InstanceGeneratorTypeScope(*values)

Bases: Enum

ENTITY = 'entity'
INSTANCE = 'instance'
class org.accellera.ipxact.v1685_2022.InstanceName(value='')

Bases: object

An instance name assigned to subcomponent instances and contained channels, that is unique within the parent component.

Parameters:

value (str)

value: str
class org.accellera.ipxact.v1685_2022.Interconnection(name=None, display_name=None, short_description=None, description=None, active_interface=<factory>, hier_interface=<factory>, vendor_extensions=None, id=None)

Bases: object

Describes a connection between two active (not monitor) busInterfaces.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • active_interface – Describes one interface of the interconnection. The componentInterfaceRef and busRef attributes indicate the instance name and bus interface name of one end of the connection. This interface can be connected to one or more additional active and/or hierarchical interfaces, or to one or more hierarchical interfaces or to one or more monitor interfaces. The connected interfaces are all contained within the choice element below.

  • hier_interface

  • vendor_extensions

  • id

Parameters:
active_interface: Iterable[ActiveInterface]
description: Description | None
display_name: DisplayName | None
hier_interface: Iterable[HierInterfaceType]
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.Interconnections(interconnection=<factory>, monitor_interconnection=<factory>)

Bases: object

Connections between internal sub components.

Parameters:
interconnection: Iterable[Interconnection]
monitor_interconnection: Iterable[MonitorInterconnection]
class org.accellera.ipxact.v1685_2022.InterfaceType(component_instance_ref=None, bus_ref=None, id=None)

Bases: object

A representation of a component/bus interface relation; i.e. a bus interface belonging to a certain component.

Variables:

  • component_instance_ref – Reference to a component instance name.

  • bus_ref – Reference to the components bus interface

  • id

Parameters:

  • component_instance_ref (str | None)

  • bus_ref (str | None)

  • id (str | None)

bus_ref: str | None
component_instance_ref: str | None
id: str | None
class org.accellera.ipxact.v1685_2022.IpxactFileType(vlnv=None, name=None, description=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • vlnv – VLNV of the IP-XACT file being cataloged.

  • name – Name of the IP-XACT file being cataloged.

  • description

  • vendor_extensions

  • id

Parameters:
description: Description | None
id: str | None
name: IpxactUri | None
vendor_extensions: VendorExtensions | None
vlnv: LibraryRefType | None
class org.accellera.ipxact.v1685_2022.IpxactFilesType(ipxact_file=<factory>)

Bases: object

Contains a list of IP-XACT files to include.

Parameters:

ipxact_file (Iterable[IpxactFileType])

ipxact_file: Iterable[IpxactFileType]
class org.accellera.ipxact.v1685_2022.IpxactUri(value='')

Bases: object

IP-XACT URI, like a standard xs:anyURI except that it can contain environment variables in the ${ } form, to be replaced by their value to provide the underlying URI.

Parameters:

value (str)

value: str
class org.accellera.ipxact.v1685_2022.IsClockEnLevel(*values)

Bases: Enum

HIGH = 'high'
LOW = 'low'
class org.accellera.ipxact.v1685_2022.IsFlowControlFlowType(*values)

Bases: Enum

BUSY = 'busy'
CREDIT_RETURN = 'credit-return'
READY = 'ready'
USER = 'user'
class org.accellera.ipxact.v1685_2022.IsPowerEnLevel(*values)

Bases: Enum

HIGH = 'high'
LOW = 'low'
class org.accellera.ipxact.v1685_2022.IsResetLevel(*values)

Bases: Enum

HIGH = 'high'
LOW = 'low'
class org.accellera.ipxact.v1685_2022.Kind(value=None, custom=None)

Bases: object

Defines the protocol type.

Defaults to tlm_base_protocol_type for TLM sockets

Parameters:

  • value (KindType | None)

  • custom (str | None)

custom: str | None
value: KindType | None
class org.accellera.ipxact.v1685_2022.KindType(*values)

Bases: Enum

CUSTOM = 'custom'
MULTI_SOCKET = 'multi_socket'
SIMPLE_SOCKET = 'simple_socket'
TLM_PORT = 'tlm_port'
TLM_SOCKET = 'tlm_socket'
class org.accellera.ipxact.v1685_2022.LanguageType(value='', strict=False)

Bases: object

Variables:

  • value

  • strict – A value of ‘true’ indicates that this value must match the language being generated for the design.

Parameters:

  • value (str)

  • strict (bool)

strict: bool
value: str
class org.accellera.ipxact.v1685_2022.Left(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: UnsignedIntExpression

The optional element left specifies the left boundary.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.LibraryRefType(vendor=None, library=None, name=None, version=None, id=None)

Bases: object

Base IP-XACT document reference type.

Contains vendor, library, name and version attributes.

Parameters:

  • vendor (str | None)

  • library (str | None)

  • name (str | None)

  • version (str | None)

  • id (str | None)

id: str | None
library: str | None
name: str | None
vendor: str | None
version: str | None
class org.accellera.ipxact.v1685_2022.LinkerCommandFile(name=None, command_line_switch=None, enable=None, generator_ref=<factory>, vendor_extensions=None, id=None)

Bases: object

Specifies a linker command file.

Variables:

  • name – Linker command file name.

  • command_line_switch – The command line switch to specify the linker command file.

  • enable – Specifies whether to generate and enable the linker command file.

  • generator_ref

  • vendor_extensions

  • id

Parameters:
command_line_switch: StringExpression | None
enable: UnsignedBitExpression | None
generator_ref: Iterable[GeneratorRef]
id: str | None
name: StringExpression | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.LoadConstraint(cell_specification=None, count=None)

Bases: object

Defines a constraint indicating the type of load on an output port.

Variables:

  • cell_specification

  • count – Indicates how many loads of the specified cell are connected. If not present, 3 is assumed.

Parameters:
cell_specification: CellSpecification | None
count: UnsignedPositiveIntExpression | None
class org.accellera.ipxact.v1685_2022.LocalAddressBankType(name=None, display_name=None, short_description=None, description=None, access_handles=None, base_address=None, address_block=<factory>, bank=<factory>, usage=None, volatile=None, access_policies=None, parameters=None, vendor_extensions=None, bank_alignment=None, id=None)

Bases: object

Top level bank the specify an address.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • base_address

  • address_block – An address block within the bank. No address information is supplied.

  • bank – A nested bank of blocks within a bank. No address information is supplied.

  • usage – Indicates the usage of this block. Possible values are ‘memory’, ‘register’ and ‘reserved’.

  • volatile

  • access_policies

  • parameters – Any additional parameters needed to describe this address block to the generators.

  • vendor_extensions

  • bank_alignment – Describes whether this bank’s blocks are aligned in ‘parallel’ or ‘serial’.

  • id

Parameters:
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_block: Iterable[BankedBlockType]
bank: Iterable[LocalBankedBankType]
bank_alignment: BankAlignmentType | None
base_address: BaseAddress | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
usage: UsageType | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
class org.accellera.ipxact.v1685_2022.LocalBankedBankType(name=None, display_name=None, short_description=None, description=None, access_handles=None, address_block=<factory>, bank=<factory>, usage=None, volatile=None, access_policies=None, parameters=None, vendor_extensions=None, bank_alignment=None, id=None)

Bases: object

Banks nested inside a bank do not specify address.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • address_block – An address block within the bank. No address information is supplied.

  • bank – A nested bank of blocks within a bank. No address information is supplied.

  • usage – Indicates the usage of this block. Possible values are ‘memory’, ‘register’ and ‘reserved’.

  • volatile

  • access_policies

  • parameters – Any additional parameters needed to describe this address block to the generators.

  • vendor_extensions

  • bank_alignment

  • id

Parameters:
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_block: Iterable[BankedBlockType]
bank: Iterable[LocalBankedBankType]
bank_alignment: BankAlignmentType | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
usage: UsageType | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
class org.accellera.ipxact.v1685_2022.LocalMemoryMapType(name=None, display_name=None, short_description=None, description=None, address_block=<factory>, bank=<factory>, vendor_extensions=None, id=None)

Bases: object

Map of address space blocks on the local memory map of a initiator bus interface.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • address_block

  • bank – Represents a bank of memory made up of address blocks or other banks. It has a bankAlignment attribute indicating whether its blocks are aligned in ‘parallel’ (occupying adjacent bit fields) or ‘serial’ (occupying contiguous addresses). Its child blocks do not contain addresses or bit offsets.

  • vendor_extensions

  • id

Parameters:
address_block: Iterable[AddressBlock]
bank: Iterable[LocalAddressBankType]
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.MemoryMapDefinitions(memory_map_definition: collections.abc.Iterable['MemoryMapDefinitions.MemoryMapDefinition'] = <factory>)

Bases: object

Parameters:

memory_map_definition (Iterable[MemoryMapDefinition])

class MemoryMapDefinition(name=None, display_name=None, short_description=None, description=None, address_block=<factory>, bank=<factory>, memory_remap=<factory>, address_unit_bits=None, shared=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • address_block

  • bank – An addressable bank of blocks within a bank definition.

  • memory_remap

  • address_unit_bits

  • shared – When the value is ‘yes’, the contents of the memoryMap are shared by all the references to this memoryMap, when the value is ‘no’ the contents of the memoryMap is not shared and when the value is ‘undefined’ (default) the sharing of the memoryMap is undefined.

  • vendor_extensions

  • id

Parameters:
address_block: Iterable[AddressBlock]
address_unit_bits: AddressUnitBits | None
bank: Iterable[AddressBankDefinitionType]
description: Description | None
display_name: DisplayName | None
id: str | None
memory_remap: Iterable[MemoryRemapDefinitionType]
name: str | None
shared: SharedType | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
memory_map_definition: Iterable[MemoryMapDefinition]
class org.accellera.ipxact.v1685_2022.MemoryMapRef(mode_ref=<factory>, memory_map_ref=None)

Bases: MemoryMapRefType

References the memory map.

The name of the memory map is kept in its memoryMapRef attribute.

Parameters:
class ModeRef(value='', id=None)

Bases: object

A reference to a mode.

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
memory_map_ref: str | None
mode_ref: Iterable['MemoryMapRefType.ModeRef']
class org.accellera.ipxact.v1685_2022.MemoryMapRefType(mode_ref=<factory>, memory_map_ref=None)

Bases: object

Base type for an element which references an memory map.

Reference is kept in an attribute rather than the text value, so that the type may be extended with child elements if necessary.

Variables:

  • mode_ref

  • memory_map_ref – A reference to a unique memory map.

Parameters:

  • mode_ref (Iterable[ModeRef])

  • memory_map_ref (str | None)

class ModeRef(value='', id=None)

Bases: object

A reference to a mode.

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
memory_map_ref: str | None
mode_ref: Iterable[ModeRef]
class org.accellera.ipxact.v1685_2022.MemoryMapType(name=None, display_name=None, short_description=None, description=None, memory_map_definition_ref=None, address_block=<factory>, bank=<factory>, subspace_map=<factory>, memory_remap=<factory>, address_unit_bits=None, shared=None, vendor_extensions=None, id=None)

Bases: object

Map of address space blocks on target target bus interface.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • memory_map_definition_ref

  • address_block

  • bank

  • subspace_map

  • memory_remap

  • address_unit_bits

  • shared – When the value is ‘yes’, the contents of the memoryMap are shared by all the references to this memoryMap, when the value is ‘no’ the contents of the memoryMap is not shared and when the value is ‘undefined’ (default) the sharing of the memoryMap is undefined.

  • vendor_extensions

  • id

Parameters:
class MemoryMapDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
address_block: Iterable[AddressBlock]
address_unit_bits: AddressUnitBits | None
bank: Iterable[Bank]
description: Description | None
display_name: DisplayName | None
id: str | None
memory_map_definition_ref: MemoryMapDefinitionRef | None
memory_remap: Iterable[MemoryRemap]
name: str | None
shared: SharedType | None
short_description: ShortDescription | None
subspace_map: Iterable[SubspaceMap]
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.MemoryMaps(memory_map=<factory>)

Bases: object

Lists all the target memory maps defined by the component.

Variables:

memory_map – The set of address blocks a bus target contributes to the bus’ address space.

Parameters:

memory_map (Iterable[MemoryMapType])

memory_map: Iterable[MemoryMapType]
class org.accellera.ipxact.v1685_2022.MemoryRemap(name=None, display_name=None, short_description=None, description=None, mode_ref=<factory>, remap_definition_ref=None, address_block=<factory>, bank=<factory>, subspace_map=<factory>, vendor_extensions=None, id=None)

Bases: MemoryRemapType

Additional memory map elements that are dependent on the component state.

Parameters:
class RemapDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
address_block: Iterable[AddressBlock]
bank: Iterable[Bank]
description: Description | None
display_name: DisplayName | None
id: str | None
mode_ref: Iterable[ModeRef]
name: str | None
remap_definition_ref: 'MemoryRemapType.RemapDefinitionRef' | None
short_description: ShortDescription | None
subspace_map: Iterable[SubspaceMap]
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.MemoryRemapDefinitionType(name=None, display_name=None, short_description=None, description=None, mode_ref=<factory>, remap_definition_ref=None, address_block=<factory>, bank=<factory>, vendor_extensions=None, id=None)

Bases: object

Map of address space blocks on a target bus interface in a specific remap state.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • mode_ref

  • remap_definition_ref

  • address_block – An address block within the bank. No address information is supplied.

  • bank – A nested bank of blocks within a bank. No address information is supplied.

  • vendor_extensions

  • id

Parameters:
class RemapDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
address_block: Iterable[AddressBlockType]
bank: Iterable[Bank]
description: Description | None
display_name: DisplayName | None
id: str | None
mode_ref: Iterable[ModeRef]
name: str | None
remap_definition_ref: RemapDefinitionRef | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.MemoryRemapDefinitions(memory_remap_definition: collections.abc.Iterable['MemoryRemapDefinitions.MemoryRemapDefinition'] = <factory>)

Bases: object

Parameters:

memory_remap_definition (Iterable[MemoryRemapDefinition])

class MemoryRemapDefinition(name=None, display_name=None, short_description=None, description=None, address_block=<factory>, bank=<factory>, address_unit_bits=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • address_block

  • bank – An addressable bank of blocks within a bank definition.

  • address_unit_bits

  • vendor_extensions

  • id

Parameters:
address_block: Iterable[AddressBlock]
address_unit_bits: AddressUnitBits | None
bank: Iterable[AddressBankDefinitionType]
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
memory_remap_definition: Iterable[MemoryRemapDefinition]
class org.accellera.ipxact.v1685_2022.MemoryRemapRef(memory_remap_ref: str | None = None)

Bases: object

Parameters:

memory_remap_ref (str | None)

memory_remap_ref: str | None
class org.accellera.ipxact.v1685_2022.MemoryRemapType(name=None, display_name=None, short_description=None, description=None, mode_ref=<factory>, remap_definition_ref=None, address_block=<factory>, bank=<factory>, subspace_map=<factory>, vendor_extensions=None, id=None)

Bases: object

Map of address space blocks on a target bus interface in a specific remap state.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • mode_ref

  • remap_definition_ref

  • address_block

  • bank

  • subspace_map

  • vendor_extensions

  • id

Parameters:
class RemapDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
address_block: Iterable[AddressBlock]
bank: Iterable[Bank]
description: Description | None
display_name: DisplayName | None
id: str | None
mode_ref: Iterable[ModeRef]
name: str | None
remap_definition_ref: RemapDefinitionRef | None
short_description: ShortDescription | None
subspace_map: Iterable[SubspaceMap]
vendor_extensions: VendorExtensions | None

Bases: object

A set of links between internal and external modes defined in the typeDefinitions document.

Variables:

mode_link – A link between one external mode and one internal mode.

Parameters:

mode_link (Iterable[ModeLink])

Bases: object

Variables:

  • external_mode_reference – Reference to a mode defined in the linked external type definitions.

  • mode_reference – Reference to a mode defined internally.

  • vendor_extensions

  • id

Parameters:
class ExternalModeReference(mode_ref=None)

Bases: object

Variables:

mode_ref – Reference to a specific mode.

Parameters:

mode_ref (str | None)

mode_ref: str | None
class ModeReference(mode_ref=None)

Bases: object

Variables:

mode_ref – Reference to a specific mode.

Parameters:

mode_ref (str | None)

mode_ref: str | None
external_mode_reference: ExternalModeReference | None
id: str | None
mode_reference: ModeReference | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.ModeRef(value='', priority=None, id=None)

Bases: object

A reference to a mode.

Parameters:

  • value (str)

  • priority (int | None)

  • id (str | None)

id: str | None
priority: int | None
value: str
class org.accellera.ipxact.v1685_2022.Model(views=None, instantiations=None, ports=None)

Bases: ModelType

Model information.

Parameters:
class Instantiations(component_instantiation=<factory>, design_instantiation=<factory>, design_configuration_instantiation=<factory>)

Bases: object

Variables:

  • component_instantiation – Component Instantiation

  • design_instantiation – Design Instantiation

  • design_configuration_instantiation – Design Configuration Instantiation

Parameters:
component_instantiation: Iterable[ComponentInstantiationType]
design_configuration_instantiation: Iterable[DesignConfigurationInstantiationType]
design_instantiation: Iterable[DesignInstantiationType]
class Ports(port: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.port.Port] = <factory>)

Bases: object

Parameters:

port (Iterable[Port])

port: Iterable[Port]
class Views(view=<factory>)

Bases: object

Variables:

view – Single view of a component

Parameters:

view (Iterable[View])

class View(name=None, display_name=None, short_description=None, description=None, env_identifier=<factory>, component_instantiation_ref=None, design_instantiation_ref=None, design_configuration_instantiation_ref=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • env_identifier – Defines the hardware environment in which this view applies. The format of the string is language:tool:vendor_extension, with each piece being optional. The language must be one of the types from ipxact:fileType. The tool values are defined by the Accellera Systems Initiative, and include generic values “*Simulation” and “*Synthesis” to imply any tool of the indicated type. Having more than one envIdentifier indicates that the view applies to multiple environments.

  • component_instantiation_ref

  • design_instantiation_ref

  • design_configuration_instantiation_ref

  • vendor_extensions

  • id

Parameters:

  • name (str | None)

  • display_name (DisplayName | None)

  • short_description (ShortDescription | None)

  • description (Description | None)

  • env_identifier (Iterable[EnvIdentifier])

  • component_instantiation_ref (str | None)

  • design_instantiation_ref (str | None)

  • design_configuration_instantiation_ref (str | None)

  • vendor_extensions (VendorExtensions | None)

  • id (str | None)

class EnvIdentifier(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
component_instantiation_ref: str | None
description: Description | None
design_configuration_instantiation_ref: str | None
design_instantiation_ref: str | None
display_name: DisplayName | None
env_identifier: Iterable[EnvIdentifier]
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
view: Iterable[View]
instantiations: 'ModelType.Instantiations' | None
ports: 'ModelType.Ports' | None
views: 'ModelType.Views' | None
class org.accellera.ipxact.v1685_2022.ModelType(views=None, instantiations=None, ports=None)

Bases: object

Model information.

Variables:

  • views – Views container

  • instantiations – Instantiations container

  • ports – Port container

Parameters:
class Instantiations(component_instantiation=<factory>, design_instantiation=<factory>, design_configuration_instantiation=<factory>)

Bases: object

Variables:

  • component_instantiation – Component Instantiation

  • design_instantiation – Design Instantiation

  • design_configuration_instantiation – Design Configuration Instantiation

Parameters:
component_instantiation: Iterable[ComponentInstantiationType]
design_configuration_instantiation: Iterable[DesignConfigurationInstantiationType]
design_instantiation: Iterable[DesignInstantiationType]
class Ports(port: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.port.Port] = <factory>)

Bases: object

Parameters:

port (Iterable[Port])

port: Iterable[Port]
class Views(view=<factory>)

Bases: object

Variables:

view – Single view of a component

Parameters:

view (Iterable[View])

class View(name=None, display_name=None, short_description=None, description=None, env_identifier=<factory>, component_instantiation_ref=None, design_instantiation_ref=None, design_configuration_instantiation_ref=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • env_identifier – Defines the hardware environment in which this view applies. The format of the string is language:tool:vendor_extension, with each piece being optional. The language must be one of the types from ipxact:fileType. The tool values are defined by the Accellera Systems Initiative, and include generic values “*Simulation” and “*Synthesis” to imply any tool of the indicated type. Having more than one envIdentifier indicates that the view applies to multiple environments.

  • component_instantiation_ref

  • design_instantiation_ref

  • design_configuration_instantiation_ref

  • vendor_extensions

  • id

Parameters:

  • name (str | None)

  • display_name (DisplayName | None)

  • short_description (ShortDescription | None)

  • description (Description | None)

  • env_identifier (Iterable[EnvIdentifier])

  • component_instantiation_ref (str | None)

  • design_instantiation_ref (str | None)

  • design_configuration_instantiation_ref (str | None)

  • vendor_extensions (VendorExtensions | None)

  • id (str | None)

class EnvIdentifier(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
component_instantiation_ref: str | None
description: Description | None
design_configuration_instantiation_ref: str | None
design_instantiation_ref: str | None
display_name: DisplayName | None
env_identifier: Iterable[EnvIdentifier]
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
view: Iterable[View]
instantiations: Instantiations | None
ports: Ports | None
views: Views | None
class org.accellera.ipxact.v1685_2022.ModifiedWriteValue(value=None, modify=None)

Bases: object

If present this element describes the modification of field data caused by a write operation.

‘oneToClear’ means that in a bitwise fashion each write data bit of a one will clear the corresponding bit in the field. ‘oneToSet’ means that in a bitwise fashion each write data bit of a one will set the corresponding bit in the field. ‘oneToToggle’ means that in a bitwise fashion each write data bit of a one will toggle the corresponding bit in the field. ‘zeroToClear’ means that in a bitwise fashion each write data bit of a zero will clear the corresponding bit in the field. ‘zeroToSet’ means that in a bitwise fashion each write data bit of a zero will set the corresponding bit in the field. ‘zeroToToggle’ means that in a bitwise fashion each write data bit of a zero will toggle the corresponding bit in the field. ‘clear’ means any write to this field clears the field. ‘set’ means any write to the field sets the field. ‘modify’ means any write to this field may modify that data. If this element is not present the write operation data is written.

Parameters:
modify: str | None
value: ModifiedWriteValueType | None
class org.accellera.ipxact.v1685_2022.ModifiedWriteValueType(*values)

Bases: Enum

CLEAR = 'clear'
MODIFY = 'modify'
ONE_TO_CLEAR = 'oneToClear'
ONE_TO_SET = 'oneToSet'
ONE_TO_TOGGLE = 'oneToToggle'
SET = 'set'
ZERO_TO_CLEAR = 'zeroToClear'
ZERO_TO_SET = 'zeroToSet'
ZERO_TO_TOGGLE = 'zeroToToggle'
class org.accellera.ipxact.v1685_2022.ModuleParameterArrays(array=<factory>)

Bases: object

Variables:

array – Specific left and right array bounds.

Parameters:

array (Iterable[Array])

class Array(left: org.accellera.ipxact.v1685_2022.left.Left | None = None, right: org.accellera.ipxact.v1685_2022.right.Right | None = None, array_id: str | None = None, id: str | None = None)

Bases: object

Parameters:

  • left (Left | None)

  • right (Right | None)

  • array_id (str | None)

  • id (str | None)

array_id: str | None
id: str | None
left: Left | None
right: Right | None
array: Iterable[Array]
class org.accellera.ipxact.v1685_2022.ModuleParameterType(name=None, display_name=None, short_description=None, description=None, vectors=None, arrays=None, value=None, vendor_extensions=None, id=None, parameter_id=None, prompt=None, choice_ref=None, order=None, config_groups=<factory>, minimum=None, maximum=None, type_value=FormatType.STRING, sign=None, prefix=None, unit=None, resolve=ModuleParameterTypeResolve.IMMEDIATE, other_attributes=<factory>, data_type=None, usage_type=ModuleParameterTypeUsageType.TYPED, data_type_definition=None, constrained=<factory>)

Bases: object

Name value pair with data type information.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • vectors

  • arrays

  • value

  • vendor_extensions

  • id

  • parameter_id – ID attribute for uniquely identifying a parameter within its document. Attribute is used to refer to this from a configurable element.

  • prompt – Provides a string used to prompt the user for user- resolved property values.

  • choice_ref – For user defined properties, refers the choice element enumerating the values to choose from.

  • order – For components with auto-generated configuration forms, the user-resolved properties with order attibutes will be presented in ascending order.

  • config_groups – Tags configurable properties so that they may be grouped together. Configurable properties with matching values for this attribute are contained in the same group. The format of this attribute is a string. There is no semantic meaning to this attribute.

  • minimum – For user-resolved properties with numeric values, this indicates the minimum value allowed. Only valid for the types: byte, shortint, int, longint, shortreal and real. The type of this value is the same as the type of the parameter- value, which is specified by the parameter-type attribute.

  • maximum – For user-resolved properties with numeric values, this indicates the maximum value allowed. Only valid for the types: byte, shortint, int, longint, shortreal and real. The type of this value is the same as the type of the parameter- value, which is specified by the parameter-type attribute.

  • type_value – Specifies the type of the value of the parameter. A parameter of type byte is resolved to an 8-bit integer value, shortint is resolved to a 16-bit integer value, int is resolved to a 32-bit integer value, longint is resolved to a 64-bit integer value, shortreal is resolved to a 32-bit floating point value, real is resolved to a 64-bit floating point value, bit is by default resolved to a one bit value, unless a vector size has been specified and the string type is resolved to a string value.

  • sign – Specify the signedness explicitly. The data types byte, shortint, int, longint default to signed. The data type bit defaults to unsigned. When setting this values for the data types string, real and shortreal the setting is ignored.

  • prefix – Defines the prefix that precedes the unit of a value. The prefix is not applied to the value (e.g. in calculations).

  • unit – Defines the unit of the value.

  • resolve – Determines how a property value can be configured.

  • other_attributes

  • data_type – The data type of the argument as pertains to the language. Example: “int”, “double”, “char *”.

  • usage_type – Indicates the type of the module parameter. Legal values are defined in the attribute enumeration list. Default value is ‘typed’.

  • data_type_definition – The dataTypeDefinition references a file, which is included in the filesetRef referenced from the componentInstantiation.

  • constrained – Indicates for which vectors and arrays the number of bits in the type declaration is fixed by referencing the vectorId and arrayId values. The values are separated by whitespace.

Parameters:
class Vectors(vector=<factory>)

Bases: object

Variables:

vector – Left and right ranges of the vector.

Parameters:

vector (Iterable[Vector])

class Vector(left: org.accellera.ipxact.v1685_2022.left.Left | None = None, right: org.accellera.ipxact.v1685_2022.right.Right | None = None, vector_id: str | None = None, id: str | None = None)

Bases: object

Parameters:

  • left (Left | None)

  • right (Right | None)

  • vector_id (str | None)

  • id (str | None)

id: str | None
left: Left | None
right: Right | None
vector_id: str | None
vector: Iterable[Vector]
arrays: ModuleParameterArrays | None
choice_ref: str | None
config_groups: Iterable[str]
constrained: Iterable[str]
data_type: str | None
data_type_definition: str | None
description: Description | None
display_name: DisplayName | None
id: str | None
maximum: str | None
minimum: str | None
name: str | None
order: float | None
other_attributes: Mapping[str, str]
parameter_id: str | None
prefix: ModuleParameterTypePrefix | None
prompt: str | None
resolve: ModuleParameterTypeResolve
short_description: ShortDescription | None
sign: SignType | None
type_value: FormatType
unit: ModuleParameterTypeUnit | None
usage_type: ModuleParameterTypeUsageType
value: Value | None
vectors: Vectors | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.ModuleParameterTypePrefix(*values)

Bases: Enum

ATTO = 'atto'
CENTI = 'centi'
DECA = 'deca'
DECI = 'deci'
EXA = 'exa'
FEMTO = 'femto'
GIGA = 'giga'
HECTO = 'hecto'
KILO = 'kilo'
MEGA = 'mega'
MICRO = 'micro'
MILLI = 'milli'
NANO = 'nano'
PETA = 'peta'
PICO = 'pico'
TERA = 'tera'
YOCTO = 'yocto'
YOTTA = 'yotta'
ZEPTO = 'zepto'
ZETTA = 'zetta'
class org.accellera.ipxact.v1685_2022.ModuleParameterTypeResolve(*values)

Bases: Enum

Determines how a parameter is resolved.

User means the value must be obtained from the user. Generated means the value will be provided by a generator.

Variables:

  • IMMEDIATE – Property content cannot be modified through configuration.

  • USER – Property content can be modified through configuration. Modifications will be saved with the design.

  • GENERATED – Generators may modify this property. Modifications get saved with the design.

GENERATED = 'generated'
IMMEDIATE = 'immediate'
USER = 'user'
class org.accellera.ipxact.v1685_2022.ModuleParameterTypeUnit(*values)

Bases: Enum

AMPERE = 'ampere'
CELSIUS = 'Celsius'
COULOMB = 'coulomb'
FARAD = 'farad'
HENRY = 'henry'
HERTZ = 'hertz'
JOULE = 'joule'
KELVIN = 'kelvin'
OHM = 'ohm'
SECOND = 'second'
SIEMENS = 'siemens'
VOLT = 'volt'
WATT = 'watt'
class org.accellera.ipxact.v1685_2022.ModuleParameterTypeUsageType(*values)

Bases: Enum

NONTYPED = 'nontyped'
RUNTIME = 'runtime'
TYPED = 'typed'
class org.accellera.ipxact.v1685_2022.MonitorInterconnection(name=None, display_name=None, short_description=None, description=None, monitored_active_interface=None, monitor_interface=<factory>, vendor_extensions=None, id=None)

Bases: object

Describes a connection from the interface of one component to any number of monitor interfaces in the design.

An active interface can be connected to unlimited number of monitor interfaces.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • monitored_active_interface – Describes an active interface of the design that all the monitors will be connected to. The componentInterfaceRef and busRef attributes indicate the instance name and bus interface name. The optional path attribute indicates the hierarchical instance name path to the component.

  • monitor_interface – Describes a list of monitor interfaces that are connected to the single active interface. The componentInterfaceRef and busRef attributes indicate the instance name and bus interface name. The optional path attribute indicates the hierarchical instance name path to the component.

  • vendor_extensions

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
id: str | None
monitor_interface: Iterable[MonitorInterfaceType]
monitored_active_interface: MonitorInterfaceType | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.MonitorInterfaceMode(*values)

Bases: Enum

INITIATOR = 'initiator'
MIRRORED_INITIATOR = 'mirroredInitiator'
MIRRORED_SYSTEM = 'mirroredSystem'
MIRRORED_TARGET = 'mirroredTarget'
SYSTEM = 'system'
TARGET = 'target'
class org.accellera.ipxact.v1685_2022.MonitorInterfaceType(component_instance_ref=None, bus_ref=None, id=None, description=None, vendor_extensions=None, path=None)

Bases: InterfaceType

Hierarchical reference to an interface being monitored or monitoring another interface.

Variables:

  • description

  • vendor_extensions

  • path – A decending hierarchical (slash separated - example x/y/z) path to the component instance containing the specified component instance in componentInterfaceRef. If not specified the componentInterfaceRef instance shall exist in the current design.

Parameters:

  • component_instance_ref (str | None)

  • bus_ref (str | None)

  • id (str | None)

  • description (Description | None)

  • vendor_extensions (VendorExtensions | None)

  • path (str | None)

bus_ref: str | None
component_instance_ref: str | None
description: Description | None
id: str | None
path: str | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.NameValuePairType(name=None, display_name=None, short_description=None, description=None, value=None, vendor_extensions=None, id=None)

Bases: object

Name and value type for use in resolvable elements.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • value

  • vendor_extensions

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
value: Value | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.OnInitiatorInitiative(*values)

Bases: Enum

BOTH = 'both'
PROVIDES = 'provides'
REQUIRES = 'requires'
class org.accellera.ipxact.v1685_2022.OnSystemInitiative(*values)

Bases: Enum

BOTH = 'both'
PROVIDES = 'provides'
REQUIRES = 'requires'
class org.accellera.ipxact.v1685_2022.OnTargetInitiative(*values)

Bases: Enum

BOTH = 'both'
PROVIDES = 'provides'
REQUIRES = 'requires'
class org.accellera.ipxact.v1685_2022.OtherClockDriver(clock_period=None, clock_pulse_offset=None, clock_pulse_value=None, clock_pulse_duration=None, id=None, clock_name=None, clock_source=None)

Bases: ClockDriverType

Describes a clock not directly associated with an input port.

The clockSource attribute can be used on these clocks to indicate the actual clock source (e.g. an output port of a clock generator cell).

Variables:

  • clock_name – Indicates the name of the clock.

  • clock_source – Indicates the name of the actual clock source (e.g. an output pin of a clock generator cell).

Parameters:
class ClockPeriod(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[float] = None, maximum: Optional[float] = None, units: org.accellera.ipxact.v1685_2022.delay_value_unit_type.DelayValueUnitType = <DelayValueUnitType.NS: 'ns'>)

Bases: RealExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

  • units (DelayValueUnitType)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
units: DelayValueUnitType
value: str
class ClockPulseDuration(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[float] = None, maximum: Optional[float] = None, units: org.accellera.ipxact.v1685_2022.delay_value_unit_type.DelayValueUnitType = <DelayValueUnitType.NS: 'ns'>)

Bases: RealExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

  • units (DelayValueUnitType)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
units: DelayValueUnitType
value: str
class ClockPulseOffset(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[float] = None, maximum: Optional[float] = None, units: org.accellera.ipxact.v1685_2022.delay_value_unit_type.DelayValueUnitType = <DelayValueUnitType.NS: 'ns'>)

Bases: RealExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

  • units (DelayValueUnitType)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
units: DelayValueUnitType
value: str
clock_name: str | None
clock_period: 'ClockDriverType.ClockPeriod' | None
clock_pulse_duration: 'ClockDriverType.ClockPulseDuration' | None
clock_pulse_offset: 'ClockDriverType.ClockPulseOffset' | None
clock_pulse_value: UnsignedBitExpression | None
clock_source: str | None
id: str | None
class org.accellera.ipxact.v1685_2022.OtherClocks(other_clock_driver=<factory>)

Bases: object

List of clocks associated with the component that are not associated with ports.

Set the clockSource attribute on the clockDriver to indicate the source of a clock not associated with a particular component port.

Parameters:

other_clock_driver (Iterable[OtherClockDriver])

other_clock_driver: Iterable[OtherClockDriver]
class org.accellera.ipxact.v1685_2022.Packets(packet: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.port_packet_type.PortPacketType] = <factory>)

Bases: PortPacketsType

Parameters:

packet (Iterable[PortPacketType])

packet: Iterable[PortPacketType]
class org.accellera.ipxact.v1685_2022.Parameter(name=None, display_name=None, short_description=None, description=None, vectors=None, arrays=None, value=None, vendor_extensions=None, id=None, parameter_id=None, prompt=None, choice_ref=None, order=None, config_groups=<factory>, minimum=None, maximum=None, type_value=FormatType.STRING, sign=None, prefix=None, unit=None, resolve=ParameterTypeResolve.IMMEDIATE, other_attributes=<factory>)

Bases: ParameterType

A name value pair.

The name is specified by the name element. The value is in the text content of the value element. This value element supports all configurability attributes.

Parameters:
arrays: ConfigurableArrays | None
choice_ref: str | None
config_groups: Iterable[str]
description: Description | None
display_name: DisplayName | None
id: str | None
maximum: str | None
minimum: str | None
name: str | None
order: float | None
other_attributes: Mapping[str, str]
parameter_id: str | None
prefix: ParameterTypePrefix | None
prompt: str | None
resolve: ParameterTypeResolve
short_description: ShortDescription | None
sign: SignType | None
type_value: FormatType
unit: ParameterTypeUnit | None
value: Value | None
vectors: Vectors | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.ParameterType(name=None, display_name=None, short_description=None, description=None, vectors=None, arrays=None, value=None, vendor_extensions=None, id=None, parameter_id=None, prompt=None, choice_ref=None, order=None, config_groups=<factory>, minimum=None, maximum=None, type_value=FormatType.STRING, sign=None, prefix=None, unit=None, resolve=ParameterTypeResolve.IMMEDIATE, other_attributes=<factory>)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • vectors

  • arrays

  • value

  • vendor_extensions

  • id

  • parameter_id – ID attribute for uniquely identifying a parameter within its document. Attribute is used to refer to this from a configurable element.

  • prompt – Provides a string used to prompt the user for user- resolved property values.

  • choice_ref – For user defined properties, refers the choice element enumerating the values to choose from.

  • order – For components with auto-generated configuration forms, the user-resolved properties with order attibutes will be presented in ascending order.

  • config_groups – Tags configurable properties so that they may be grouped together. Configurable properties with matching values for this attribute are contained in the same group. The format of this attribute is a string. There is no semantic meaning to this attribute.

  • minimum – For user-resolved properties with numeric values, this indicates the minimum value allowed. Only valid for the types: byte, shortint, int, longint, shortreal and real. The type of this value is the same as the type of the parameter- value, which is specified by the parameter-type attribute.

  • maximum – For user-resolved properties with numeric values, this indicates the maximum value allowed. Only valid for the types: byte, shortint, int, longint, shortreal and real. The type of this value is the same as the type of the parameter- value, which is specified by the parameter-type attribute.

  • type_value – Specifies the type of the value of the parameter. A parameter of type byte is resolved to an 8-bit integer value, shortint is resolved to a 16-bit integer value, int is resolved to a 32-bit integer value, longint is resolved to a 64-bit integer value, shortreal is resolved to a 32-bit floating point value, real is resolved to a 64-bit floating point value, bit is by default resolved to a one bit value, unless a vector size has been specified and the string type is resolved to a string value.

  • sign – Specify the signedness explicitly. The data types byte, shortint, int, longint default to signed. The data type bit defaults to unsigned. When setting this values for the data types string, real and shortreal the setting is ignored.

  • prefix – Defines the prefix that precedes the unit of a value. The prefix is not applied to the value (e.g. in calculations).

  • unit – Defines the unit of the value.

  • resolve – Determines how a property value can be configured.

  • other_attributes

Parameters:
arrays: ConfigurableArrays | None
choice_ref: str | None
config_groups: Iterable[str]
description: Description | None
display_name: DisplayName | None
id: str | None
maximum: str | None
minimum: str | None
name: str | None
order: float | None
other_attributes: Mapping[str, str]
parameter_id: str | None
prefix: ParameterTypePrefix | None
prompt: str | None
resolve: ParameterTypeResolve
short_description: ShortDescription | None
sign: SignType | None
type_value: FormatType
unit: ParameterTypeUnit | None
value: Value | None
vectors: Vectors | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.ParameterTypePrefix(*values)

Bases: Enum

ATTO = 'atto'
CENTI = 'centi'
DECA = 'deca'
DECI = 'deci'
EXA = 'exa'
FEMTO = 'femto'
GIGA = 'giga'
HECTO = 'hecto'
KILO = 'kilo'
MEGA = 'mega'
MICRO = 'micro'
MILLI = 'milli'
NANO = 'nano'
PETA = 'peta'
PICO = 'pico'
TERA = 'tera'
YOCTO = 'yocto'
YOTTA = 'yotta'
ZEPTO = 'zepto'
ZETTA = 'zetta'
class org.accellera.ipxact.v1685_2022.ParameterTypeResolve(*values)

Bases: Enum

Determines how a parameter is resolved.

User means the value must be obtained from the user. Generated means the value will be provided by a generator.

Variables:

  • IMMEDIATE – Property content cannot be modified through configuration.

  • USER – Property content can be modified through configuration. Modifications will be saved with the design.

  • GENERATED – Generators may modify this property. Modifications get saved with the design.

GENERATED = 'generated'
IMMEDIATE = 'immediate'
USER = 'user'
class org.accellera.ipxact.v1685_2022.ParameterTypeUnit(*values)

Bases: Enum

AMPERE = 'ampere'
CELSIUS = 'Celsius'
COULOMB = 'coulomb'
FARAD = 'farad'
HENRY = 'henry'
HERTZ = 'hertz'
JOULE = 'joule'
KELVIN = 'kelvin'
OHM = 'ohm'
SECOND = 'second'
SIEMENS = 'siemens'
VOLT = 'volt'
WATT = 'watt'
class org.accellera.ipxact.v1685_2022.Parameters(parameter=<factory>)

Bases: object

A collection of parameters and associated value assertions.

Parameters:

parameter (Iterable[Parameter])

parameter: Iterable[Parameter]
class org.accellera.ipxact.v1685_2022.PartSelect(range=<factory>, indices=None, id=None)

Bases: object

Bit range definition.

Parameters:

  • range (Iterable[Range])

  • indices (Indices | None)

  • id (str | None)

id: str | None
indices: Indices | None
range: Iterable[Range]
class org.accellera.ipxact.v1685_2022.PathSegmentType(value='', other_attributes=<factory>, id=None)

Bases: UnresolvedStringExpression

Identifies one level of hierarchy in the view specifed by viewNameRef.

This is a simple name and optionally some indices into a multi dimensional element.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • id (str | None)

id: str | None
other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.Payload(name=None, type_value=None, extension=None, vendor_extensions=None)

Bases: object

Defines the structure of data transported by this port.

Variables:

  • name – Defines the name of the payload. For example: TLM2 or TLM1

  • type_value – Defines the type of the payload.

  • extension – Defines the name of the payload extension. If attribute is not specified, it is by default optional.

  • vendor_extensions

Parameters:
class Extension(value='', mandatory=False)

Bases: object

Variables:

  • value

  • mandatory – True if the payload extension is mandatory.

Parameters:

  • value (str)

  • mandatory (bool)

mandatory: bool
value: str
extension: Extension | None
name: str | None
type_value: PayloadType | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.PayloadType(*values)

Bases: Enum

GENERIC = 'generic'
SPECIFIC = 'specific'
class org.accellera.ipxact.v1685_2022.Phase(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: RealExpression

This is an non-negative floating point number that is used to sequence when a generator is run.

The generators are run in order starting with zero. There may be multiple generators with the same phase number. In this case, the order should not matter with respect to other generators at the same phase. If no phase number is given the generator will be considered in the “last” phase and these generators will be run in the order in which they are encountered while processing generator elements.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.Port(name=None, display_name=None, short_description=None, description=None, wire=None, transactional=None, structured=None, field_maps=None, arrays=None, access=None, parameters=None, vendor_extensions=None, id=None)

Bases: PortType

Describes port characteristics.

Parameters:
access: PortAccessType1 | None
arrays: Arrays | None
description: Description | None
display_name: DisplayName | None
field_maps: FieldMaps | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
structured: PortStructuredType | None
transactional: PortTransactionalType | None
vendor_extensions: VendorExtensions | None
wire: PortWireType | None
class org.accellera.ipxact.v1685_2022.PortAccessHandle(view_ref=<factory>, indices=None, slices=None, vendor_extensions=None, force=True, id=None)

Bases: object

Variables:

  • view_ref – A list of views this accessHandle is applicable to. Note this element is optional, if it is not present the accessHandle applies to all views.

  • indices – For a multi dimensional IP-XACT object, indices can be specified to select the element the accessHandle applies to. This is an index into a multi-dimensional array and follows C-semantics for indexing.

  • slices

  • vendor_extensions

  • force

  • id

Parameters:
class Indices(index=<factory>)

Bases: object

Variables:

index – An index into the IP-XACT object.

Parameters:

index (Iterable[Index])

class Index(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[int] = None, maximum: Optional[int] = None, id: Optional[str] = None)

Bases: UnsignedIntExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

  • id (str | None)

id: str | None
maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str
index: Iterable[Index]
class ViewRef(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
force: bool
id: str | None
indices: Indices | None
slices: PortSlicesType | None
vendor_extensions: VendorExtensions | None
view_ref: Iterable[ViewRef]
class org.accellera.ipxact.v1685_2022.PortAccessType(value=None)

Bases: object

Indicates how a netlister accesses a port.

‘ref’ means accessed by reference (default) and ‘ptr’ means accessed by pointer.

Parameters:

value (SimplePortAccessType | None)

value: SimplePortAccessType | None
class org.accellera.ipxact.v1685_2022.PortAccessType1(port_access_type=None, access_handles=None)

Bases: object

Variables:

  • port_access_type – Indicates how a netlister accesses a port. ‘ref’ means accessed by reference (default) and ‘ptr’ means accessed through a pointer.

  • access_handles

Parameters:

  • port_access_type (PortAccessType | None)

  • access_handles (AccessHandles | None)

access_handles: AccessHandles | None
port_access_type: PortAccessType | None
class org.accellera.ipxact.v1685_2022.PortPacketFieldType(name=None, display_name=None, short_description=None, description=None, width=None, value=None, endianness=None, qualifier=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • width

  • value

  • endianness

  • qualifier – The type of information this port carries a wire port can carry both address and data, but may not mix this with a clock or reset.

  • vendor_extensions

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
endianness: EndianessType | None
id: str | None
name: str | None
qualifier: QualifierType | None
short_description: ShortDescription | None
value: UnsignedBitVectorExpression | None
vendor_extensions: VendorExtensions | None
width: UnresolvedUnsignedPositiveIntExpression | None
class org.accellera.ipxact.v1685_2022.PortPacketFieldsType(packet_field: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.port_packet_field_type.PortPacketFieldType] = <factory>)

Bases: object

Parameters:

packet_field (Iterable[PortPacketFieldType])

packet_field: Iterable[PortPacketFieldType]
class org.accellera.ipxact.v1685_2022.PortPacketType(name=None, display_name=None, short_description=None, description=None, endianness=None, packet_fields=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • endianness

  • packet_fields

  • vendor_extensions

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
endianness: EndianessType | None
id: str | None
name: str | None
packet_fields: PortPacketFieldsType | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.PortPacketsType(packet: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.port_packet_type.PortPacketType] = <factory>)

Bases: object

Parameters:

packet (Iterable[PortPacketType])

packet: Iterable[PortPacketType]
class org.accellera.ipxact.v1685_2022.PortPathSegmentType(value='', other_attributes=<factory>, id=None)

Bases: StringExpression

Identifies one level of hierarchy in the view specifed by viewNameRef.

This is a simple name and optionally some indices into a multi dimensional element.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • id (str | None)

id: str | None
other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.PortSliceType(path_segments=None, range=None, id=None)

Bases: object

Contains the HDL path information for a slice of the IP-XACT object.

Variables:

  • path_segments – An ordered list of pathSegment elements. When concatenated with a desired separator the elements in this form a HDL path for the parent slice into the referenced view.

  • range – A range to be applied to the concatenation of the above path segments

  • id

Parameters:
class PathSegments(path_segment: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.port_path_segment_type.PortPathSegmentType] = <factory>)

Bases: object

Parameters:

path_segment (Iterable[PortPathSegmentType])

path_segment: Iterable[PortPathSegmentType]
id: str | None
path_segments: PathSegments | None
range: Range | None
class org.accellera.ipxact.v1685_2022.PortSlicesType(slice=<factory>)

Bases: object

Each slice specifies the HDL path for part of the parent IP-XACT object.

The slices must be concatenated to calculate the entire path. If there is only one slice, it is assumed to be the path for the entire IP-XACT object.

Variables:

slice – The HDL path for a slice of the IP-XACT object.

Parameters:

slice (Iterable[PortSliceType])

slice: Iterable[PortSliceType]
class org.accellera.ipxact.v1685_2022.PortStructuredType(struct=None, union=None, interface=None, vectors=None, sub_ports=None, struct_port_type_defs=None, packed=True)

Bases: object

Variables:

  • struct

  • union

  • interface

  • vectors – Vectored information.

  • sub_ports

  • struct_port_type_defs

  • packed – When not present or set to ‘true’ indicates that this structured port is ‘packed’. If present and set to ‘false’, indicates that this structured port is ‘unpacked’.

Parameters:
class Interface(phantom: bool | None = None)

Bases: object

Parameters:

phantom (bool | None)

phantom: bool | None
class Struct(direction=None)

Bases: object

Variables:

direction – The direction of a wire style port. The basic directions for a port are ‘in’ for input ports, ‘out’ for output port and ‘inout’ for bidirectional and tristate ports. A value of ‘phantom’ is also allowed and define a port that exist on the IP-XACT component but not on the HDL model.

Parameters:

direction (ComponentPortDirectionType | None)

direction: ComponentPortDirectionType | None
class SubPorts(sub_port: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.sub_port_type.SubPortType] = <factory>)

Bases: object

Parameters:

sub_port (Iterable[SubPortType])

sub_port: Iterable[SubPortType]
class UnionType(direction=None)

Bases: object

Variables:

direction – The direction of a wire style port. The basic directions for a port are ‘in’ for input ports, ‘out’ for output port and ‘inout’ for bidirectional and tristate ports. A value of ‘phantom’ is also allowed and define a port that exist on the IP-XACT component but not on the HDL model.

Parameters:

direction (ComponentPortDirectionType | None)

direction: ComponentPortDirectionType | None
interface: Interface | None
packed: bool
struct: Struct | None
struct_port_type_defs: StructPortTypeDefs | None
sub_ports: SubPorts | None
union: UnionType | None
vectors: ExtendedVectorsType | None
class org.accellera.ipxact.v1685_2022.PortTransactionalType(initiative=None, kind=None, bus_width=None, qualifier=None, protocol=None, trans_type_defs=None, connection=None, power_constraints=None, all_logical_initiatives_allowed=False)

Bases: object

Transactional port type.

Variables:

  • initiative – Defines how the port accesses this service.

  • kind – Define the kind of transactional port

  • bus_width – Defines the bus width in bits.This can be the result of an expression.

  • qualifier – The type of information this port carries A transactional port can carry both address and data information.

  • protocol – Defines the protocol type. Defaults to tlm_base_protocol_type for TLM sockets

  • trans_type_defs – Definition of the port type expressed in the default language for this port (i.e. SystemC or SystemV).

  • connection – Bounds number of legal connections.

  • power_constraints – Wire port power constraints.

  • all_logical_initiatives_allowed – True if logical ports with different initiatives from the physical port initiative may be mapped onto this port. Forbidden for phantom ports, which always allow logical ports with all initiatives value to be mapped onto the physical port. Also ignored for “both” ports, since any logical port may be mapped to a physical “both” port.

Parameters:
class Connection(max_connections=None, min_connections=None)

Bases: object

Variables:

  • max_connections – Indicates the maximum number of connections this port supports. If this element is not present or set to 0 it implies an unbounded number of allowed connections.

  • min_connections – Indicates the minimum number of connections this port supports. If this element is not present, the minimum number of allowed connections is 1.

Parameters:
max_connections: UnsignedIntExpression | None
min_connections: UnsignedIntExpression | None
class PowerConstraints(power_constraint=<factory>)

Bases: object

Variables:

power_constraint – Single wire port set of power constraints.

Parameters:

power_constraint (Iterable[TransactionalPowerConstraintType])

power_constraint: Iterable[TransactionalPowerConstraintType]
all_logical_initiatives_allowed: bool
bus_width: BusWidth | None
connection: Connection | None
initiative: Initiative | None
kind: Kind | None
power_constraints: PowerConstraints | None
protocol: Protocol | None
qualifier: QualifierType | None
trans_type_defs: TransTypeDefs | None
class org.accellera.ipxact.v1685_2022.PortType(name=None, display_name=None, short_description=None, description=None, wire=None, transactional=None, structured=None, field_maps=None, arrays=None, access=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

A port description, giving a name and an access type for high level ports.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • wire – Defines a port whose type resolves to simple bits.

  • transactional – Defines a port that implements or uses a service that can be implemented with functions or methods.

  • structured – Represents a port that has subport structure.

  • field_maps

  • arrays

  • access – Port access characteristics.

  • parameters

  • vendor_extensions

  • id

Parameters:
access: PortAccessType1 | None
arrays: Arrays | None
description: Description | None
display_name: DisplayName | None
field_maps: FieldMaps | None
id: str | None
name: str | None
parameters: Parameters | None
short_description: ShortDescription | None
structured: PortStructuredType | None
transactional: PortTransactionalType | None
vendor_extensions: VendorExtensions | None
wire: PortWireType | None
class org.accellera.ipxact.v1685_2022.PortWireType(direction=None, qualifier=None, vectors=None, wire_type_defs=None, domain_type_defs=None, signal_type_defs=None, drivers=None, constraint_sets=None, power_constraints=None, all_logical_directions_allowed=False)

Bases: object

Wire port type for a component.

Variables:

  • direction – The direction of a wire style port. The basic directions for a port are ‘in’ for input ports, ‘out’ for output port and ‘inout’ for bidirectional and tristate ports. A value of ‘phantom’ is also allowed and define a port that exist on the IP-XACT component but not on the HDL model.

  • qualifier – The type of information this port carries a wire port can carry both address and data, but may not mix this with a clock or reset.

  • vectors – Vectored information.

  • wire_type_defs

  • domain_type_defs

  • signal_type_defs

  • drivers

  • constraint_sets

  • power_constraints – Wire port power constraints.

  • all_logical_directions_allowed – True if logical ports with different directions from the physical port direction may be mapped onto this port. Forbidden for phantom ports, which always allow logical ports with all direction value to be mapped onto the physical port. Also ignored for inout ports, since any logical port maybe mapped to a physical inout port.

Parameters:
class PowerConstraints(power_constraint=<factory>)

Bases: object

Variables:

power_constraint – Single wire port set of power constraints.

Parameters:

power_constraint (Iterable[WirePowerConstraintType])

power_constraint: Iterable[WirePowerConstraintType]
all_logical_directions_allowed: bool
constraint_sets: ConstraintSets | None
direction: ComponentPortDirectionType | None
domain_type_defs: DomainTypeDefs | None
drivers: Drivers | None
power_constraints: PowerConstraints | None
qualifier: QualifierType | None
signal_type_defs: SignalTypeDefs | None
vectors: ExtendedVectorsType | None
wire_type_defs: WireTypeDefs | None

Bases: object

Variables:

power_domain_link – A power domain link to one external power domain and one or more internal power domains.

Parameters:

power_domain_link (Iterable[PowerDomainLink])

Bases: object

Variables:

  • external_power_domain_reference – Reference to a power domain defined on the top component.

  • internal_power_domain_reference – Reference to a power domain defined on an instance

  • id

Parameters:
class InternalPowerDomainReference(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
external_power_domain_reference: StringExpression | None
id: str | None
internal_power_domain_reference: Iterable[InternalPowerDomainReference]
class org.accellera.ipxact.v1685_2022.PowerDomainRef(value='')

Bases: object

Power domain.

It is the user’s responsibility to ensure it matches an existing power domain in UPF/CPF file.

Parameters:

value (str)

value: str
class org.accellera.ipxact.v1685_2022.Presence(value=PresenceType.OPTIONAL)

Bases: object

If this element is present, the existance of the port is controlled by the specified value.

valid values are ‘illegal’, ‘required’ and ‘optional’.

Parameters:

value (PresenceType)

value: PresenceType
class org.accellera.ipxact.v1685_2022.PresenceType(*values)

Bases: Enum

ILLEGAL = 'illegal'
OPTIONAL = 'optional'
REQUIRED = 'required'
class org.accellera.ipxact.v1685_2022.Protocol(protocol_type=None, payload=None)

Bases: object

Defines the protocol type.

Defaults to tlm_base_protocol_type for TLM sockets

Parameters:
class ProtocolType(value: org.accellera.ipxact.v1685_2022.protocol_type_type.ProtocolTypeType | None = None, custom: str | None = None)

Bases: object

Parameters:
custom: str | None
value: ProtocolTypeType | None
payload: Payload | None
protocol_type: ProtocolType | None
class org.accellera.ipxact.v1685_2022.ProtocolTypeType(*values)

Bases: Enum

CUSTOM = 'custom'
TLM = 'tlm'
class org.accellera.ipxact.v1685_2022.QualifiedExpression(value='', other_attributes=<factory>)

Bases: ComplexBaseExpression

Represents an expression qualified by an accompanying type.

It supports an expression value.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.QualifierType(is_address=None, is_data=None, is_clock=None, is_reset=None, is_valid=None, is_interrupt=None, is_clock_en=None, is_power_en=None, is_opcode=None, is_protection=None, is_flow_control=None, is_user=None, is_request=None, is_response=None, id=None)

Bases: object

Variables:

  • is_address – If this element is present, the port contains address information.

  • is_data – If this element is present, the port contains data information.

  • is_clock – If this element is present, the port contains only clock information.

  • is_reset – If this element is present, the port contains only reset information.

  • is_valid – If this element is present, the port signifies that the data on the interface is currently valid

  • is_interrupt – If this element is present, the port contains only interrupt information.

  • is_clock_en – If this element is present, the port indicates that an associated conditional clock should be turned on.

  • is_power_en – If this element is present, the port indicates that an associated power domain should be activated.

  • is_opcode – If this element is present, the port determines the interpretation of other signals in the interface.

  • is_protection – If this element is present, the port implements a protection signal.

  • is_flow_control – If this element is present, the port is used by the interface’s flow control mechanism.

  • is_user – If this element is present, the port is used for user defined behavior.

  • is_request – If this element is present, the port implements a request signal.

  • is_response – If this element is present, the port implements a response signal.

  • id

Parameters:

  • is_address (bool | None)

  • is_data (bool | None)

  • is_clock (bool | None)

  • is_reset (IsReset | None)

  • is_valid (bool | None)

  • is_interrupt (bool | None)

  • is_clock_en (IsClockEn | None)

  • is_power_en (IsPowerEn | None)

  • is_opcode (bool | None)

  • is_protection (bool | None)

  • is_flow_control (IsFlowControl | None)

  • is_user (IsUser | None)

  • is_request (bool | None)

  • is_response (bool | None)

  • id (str | None)

class IsClockEn(value=None, level=None)

Bases: object

Variables:

  • value

  • level – Assertion level

Parameters:
level: IsClockEnLevel | None
value: bool | None
class IsFlowControl(value=None, flow_type=None, user=None)

Bases: object

Variables:

  • value

  • flow_type – Controlled flow type

  • user – User flow type information

Parameters:
flow_type: IsFlowControlFlowType | None
user: str | None
value: bool | None
class IsPowerEn(value=None, level=None, power_domain_ref=None)

Bases: object

Variables:

  • value

  • level – Assertion level

  • power_domain_ref – PowerDomain references

Parameters:

  • value (bool | None)

  • level (IsPowerEnLevel | None)

  • power_domain_ref (str | None)

level: IsPowerEnLevel | None
power_domain_ref: str | None
value: bool | None
class IsReset(value=None, level=None)

Bases: object

Variables:

  • value

  • level – Assertion level

Parameters:
level: IsResetLevel | None
value: bool | None
class IsUser(value=None, user=None)

Bases: object

Variables:

  • value

  • user – User behaviour

Parameters:

  • value (bool | None)

  • user (str | None)

user: str | None
value: bool | None
id: str | None
is_address: bool | None
is_clock: bool | None
is_clock_en: IsClockEn | None
is_data: bool | None
is_flow_control: IsFlowControl | None
is_interrupt: bool | None
is_opcode: bool | None
is_power_en: IsPowerEn | None
is_protection: bool | None
is_request: bool | None
is_reset: IsReset | None
is_response: bool | None
is_user: IsUser | None
is_valid: bool | None
class org.accellera.ipxact.v1685_2022.Range(left=None, right=None)

Bases: object

Left and right bound of a reference into a vector.

Parameters:
left: Left | None
right: Right | None
class org.accellera.ipxact.v1685_2022.ReadAction(value=None, modify=None)

Bases: object

A list of possible actions for a read to set the field after the read.

‘clear’ means that after a read the field is cleared. ‘set’ means that after a read the field is set. ‘modify’ means after a read the field is modified. If not present the field value is not modified after a read.

Parameters:
modify: str | None
value: ReadActionType | None
class org.accellera.ipxact.v1685_2022.ReadActionType(*values)

Bases: Enum

CLEAR = 'clear'
MODIFY = 'modify'
SET = 'set'
class org.accellera.ipxact.v1685_2022.ReadResponse(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>)

Bases: UnsignedBitVectorExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.RealExpression(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: ComplexBaseExpression

A real which supports an expression value.

Variables:

  • minimum – For elements which can be specified using expression which are supposed to be resolved to a real value, this indicates the minimum value allowed.

  • maximum – For elements which can be specified using expression which are supposed to be resolved to a real value, this indicates the maximum value allowed.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.RegisterDefinitions(register_definition: collections.abc.Iterable['RegisterDefinitions.RegisterDefinition'] = <factory>)

Bases: object

Parameters:

register_definition (Iterable[RegisterDefinition])

class RegisterDefinition(name=None, display_name=None, short_description=None, description=None, type_identifier=None, size=None, volatile=None, access_policies=None, field_value=<factory>, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • type_identifier – Identifier name used to indicate that multiple register elements contain the exact same information for the elements in the registerDefinitionGroup.

  • size – Width of the register in bits.

  • volatile

  • access_policies

  • field_value – Describes individual bit fields within the register.

  • vendor_extensions

  • id

Parameters:
access_policies: AccessPolicies | None
description: Description | None
display_name: DisplayName | None
field_value: Iterable[FieldType]
id: str | None
name: str | None
short_description: ShortDescription | None
size: UnsignedPositiveIntExpression | None
type_identifier: str | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
register_definition: Iterable[RegisterDefinition]
class org.accellera.ipxact.v1685_2022.RegisterFile(name=None, display_name=None, short_description=None, description=None, access_handles=None, array=None, address_offset=None, register_file_definition_ref=None, type_identifier=None, range=None, access_policies=None, register=<factory>, register_file=<factory>, parameters=None, vendor_extensions=None, id=None)

Bases: object

A structure of registers and register files.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • array

  • address_offset – Offset from the address block’s baseAddress or the containing register file’s addressOffset, expressed as the number of addressUnitBits from the containing memoryMap or localMemoryMap.

  • register_file_definition_ref

  • type_identifier – Identifier name used to indicate that multiple registerFile elements contain the exact same information except for the elements in the registerFileInstanceGroup.

  • range – The range of a register file. Expressed as the number of addressable units accessible to the block. Specified in units of addressUnitBits.

  • access_policies

  • register – A single register

  • register_file – A structure of registers and register files

  • parameters

  • vendor_extensions

  • id

Parameters:
class Register(name=None, display_name=None, short_description=None, description=None, access_handles=None, array=None, address_offset=None, register_definition_ref=None, type_identifier=None, size=None, volatile=None, access_policies=None, field_value=<factory>, alternate_registers=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • array

  • address_offset – Offset from the address block’s baseAddress or the containing register file’s addressOffset, expressed as the number of addressUnitBits from the containing memoryMap or localMemoryMap.

  • register_definition_ref

  • type_identifier – Identifier name used to indicate that multiple register elements contain the exact same information for the elements in the registerDefinitionGroup.

  • size – Width of the register in bits.

  • volatile

  • access_policies

  • field_value – Describes individual bit fields within the register.

  • alternate_registers

  • parameters

  • vendor_extensions

  • id

Parameters:
class RegisterDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_offset: UnsignedLongintExpression | None
alternate_registers: AlternateRegisters | None
array: Array | None
description: Description | None
display_name: DisplayName | None
field_value: Iterable[FieldType]
id: str | None
name: str | None
parameters: Parameters | None
register_definition_ref: RegisterDefinitionRef | None
short_description: ShortDescription | None
size: UnsignedPositiveIntExpression | None
type_identifier: str | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
class RegisterFileDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_offset: UnsignedLongintExpression | None
array: Array | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
parameters: Parameters | None
range: UnsignedPositiveLongintExpression | None
register: Iterable[Register]
register_file: Iterable[RegisterFile]
register_file_definition_ref: RegisterFileDefinitionRef | None
short_description: ShortDescription | None
type_identifier: str | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.RegisterFileDefinitions(register_file_definition: collections.abc.Iterable['RegisterFileDefinitions.RegisterFileDefinition'] = <factory>)

Bases: object

Parameters:

register_file_definition (Iterable[RegisterFileDefinition])

class RegisterFileDefinition(name=None, display_name=None, short_description=None, description=None, type_identifier=None, range=None, access_policies=None, register=<factory>, register_file=<factory>, address_unit_bits=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • type_identifier – Identifier name used to indicate that multiple registerFile elements contain the exact same information except for the elements in the registerFileInstanceGroup.

  • range – The range of a register file. Expressed as the number of addressable units accessible to the block. Specified in units of addressUnitBits.

  • access_policies

  • register – A single register

  • register_file – A structure of registers and register files

  • address_unit_bits

  • vendor_extensions

  • id

Parameters:
class Register(name=None, display_name=None, short_description=None, description=None, access_handles=None, array=None, address_offset=None, register_definition_ref=None, type_identifier=None, size=None, volatile=None, access_policies=None, field_value=<factory>, alternate_registers=None, parameters=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • access_handles

  • array

  • address_offset – Offset from the address block’s baseAddress or the containing register file’s addressOffset, expressed as the number of addressUnitBits from the containing memoryMap or localMemoryMap.

  • register_definition_ref

  • type_identifier – Identifier name used to indicate that multiple register elements contain the exact same information for the elements in the registerDefinitionGroup.

  • size – Width of the register in bits.

  • volatile

  • access_policies

  • field_value – Describes individual bit fields within the register.

  • alternate_registers

  • parameters

  • vendor_extensions

  • id

Parameters:
class RegisterDefinitionRef(value: str = '', type_definitions: str | None = None)

Bases: object

Parameters:

  • value (str)

  • type_definitions (str | None)

type_definitions: str | None
value: str
access_handles: AccessHandles | None
access_policies: AccessPolicies | None
address_offset: UnsignedLongintExpression | None
alternate_registers: AlternateRegisters | None
array: Array | None
description: Description | None
display_name: DisplayName | None
field_value: Iterable[FieldType]
id: str | None
name: str | None
parameters: Parameters | None
register_definition_ref: RegisterDefinitionRef | None
short_description: ShortDescription | None
size: UnsignedPositiveIntExpression | None
type_identifier: str | None
vendor_extensions: VendorExtensions | None
volatile: Volatile | None
access_policies: AccessPolicies | None
address_unit_bits: AddressUnitBits | None
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
range: UnsignedPositiveLongintExpression | None
register: Iterable[Register]
register_file: Iterable[RegisterFile]
short_description: ShortDescription | None
type_identifier: str | None
vendor_extensions: VendorExtensions | None
register_file_definition: Iterable[RegisterFileDefinition]
class org.accellera.ipxact.v1685_2022.RegisterFileRef(indices: org.accellera.ipxact.v1685_2022.indices.Indices | None = None, register_file_ref: str | None = None, id: str | None = None)

Bases: object

Parameters:

  • indices (Indices | None)

  • register_file_ref (str | None)

  • id (str | None)

id: str | None
indices: Indices | None
register_file_ref: str | None
class org.accellera.ipxact.v1685_2022.RegisterRef(indices: org.accellera.ipxact.v1685_2022.indices.Indices | None = None, register_ref: str | None = None)

Bases: object

Parameters:

  • indices (Indices | None)

  • register_ref (str | None)

indices: Indices | None
register_ref: str | None
class org.accellera.ipxact.v1685_2022.RequiresDriver(value=False, driver_type=RequiresDriverDriverType.ANY)

Bases: object

Specifies if a port requires a driver.

Default is false. The attribute driverType can further qualify what type of driver is required. Undefined behaviour if direction is not input or inout. Driver type any indicates that any unspecified type of driver must be connected

Variables:

  • value

  • driver_type – Defines the type of driver that is required. The default is any type of driver. The 2 other options are a clock type driver or a singleshot type driver.

Parameters:
driver_type: RequiresDriverDriverType
value: bool
class org.accellera.ipxact.v1685_2022.RequiresDriverDriverType(*values)

Bases: Enum

ANY = 'any'
CLOCK = 'clock'
SINGLE_SHOT = 'singleShot'
class org.accellera.ipxact.v1685_2022.Reset(value=None, mask=None, reset_type_ref=None, id=None)

Bases: object

Register value at reset.

Variables:

  • value – The value itself.

  • mask – Mask to be anded with the value before comparing to the reset value.

  • reset_type_ref – Reference to a user defined resetType. Assumed to be HARD if not present.

  • id

Parameters:
id: str | None
mask: UnsignedBitVectorExpression | None
reset_type_ref: str | None
value: UnsignedBitVectorExpression | None

Bases: object

A set of links between internal and external resetTypes defined in the typeDefinitions document.

Variables:

reset_type_link – A link between one external reset type and one internal resetType.

Parameters:

reset_type_link (Iterable[ResetTypeLink])

Bases: object

Variables:

  • external_reset_type_reference – Reference to a resetType defined in the linked external type definitions.

  • reset_type_reference – Reference to a resetType defined internally.

  • vendor_extensions

  • id

Parameters:
class ExternalResetTypeReference(reset_type_ref=None)

Bases: object

Variables:

reset_type_ref – Reference to a specific resetType.

Parameters:

reset_type_ref (str | None)

reset_type_ref: str | None
class ResetTypeReference(reset_type_ref=None)

Bases: object

Variables:

reset_type_ref – Reference to a specific resetType

Parameters:

reset_type_ref (str | None)

reset_type_ref: str | None
external_reset_type_reference: ExternalResetTypeReference | None
id: str | None
reset_type_reference: ResetTypeReference | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.ReturnTypeType(*values)

Bases: Enum

INT = 'int'
VOID = 'void'
class org.accellera.ipxact.v1685_2022.Right(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: UnsignedIntExpression

The optional element right specifies the right boundary.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.ServiceTypeDef(type_name=None, type_definition=<factory>, type_parameters=None, id=None)

Bases: object

Definition of a single service type defintion.

Variables:

  • type_name – The name of the service type. Can be any predefined type such as booean or integer or any user-defined type such as addr_type or data_type.

  • type_definition – Where the definition of the type is contained if the type if not part of the language. For SystemC and SystemVerilog it is the include file containing the type definition.

  • type_parameters

  • id

Parameters:
class TypeDefinition(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
class TypeName(value='', implicit=False)

Bases: object

Variables:

  • value

  • implicit – Defines that the typeName supplied for this service is implicit and a netlister should not declare this service in a language specific top-level netlist

Parameters:

  • value (str)

  • implicit (bool)

implicit: bool
value: str
id: str | None
type_definition: Iterable[TypeDefinition]
type_name: TypeName | None
type_parameters: TypeParameters | None
class org.accellera.ipxact.v1685_2022.SharedType(*values)

Bases: Enum

The sharedness of the memoryMap content.

NO = 'no'
UNDEFINED = 'undefined'
YES = 'yes'
class org.accellera.ipxact.v1685_2022.ShortDescription(value='')

Bases: object

Brief description suitable for titles, software comments and pop-up windows.

Being a SystemVerilog expression the text can be constructed using parameters, e.g, by concatentation or $sformatf().

Parameters:

value (str)

value: str
class org.accellera.ipxact.v1685_2022.SignType(*values)

Bases: Enum

This is an indication of the signedness of the value.

SIGNED = 'signed'
UNSIGNED = 'unsigned'
class org.accellera.ipxact.v1685_2022.SignalTypeDef(signal_type=None, view_ref=<factory>, id=None)

Bases: object

Definition of a single signal type defintion that can relate to multiple views.

Variables:

  • signal_type – defines the signal type for the port. Continuous- conservative is a signal which is continuous in time and quantity, where the quantity represents voltage and current to capture the conservative behavior of an electrical network (i. e. Kirchhoff’s Laws apply), and which has no direction. Continuous-non-conservative is a directed signal which is continuous in time and quantity, where the quantity represents either a voltage or a current (often called signal flow). In this case it only captures the non-conservative behavior of a set of interconnected components. Discrete is a directed sampled signal which is time-discrete and value-continuous (the value may also be quantified), where the value represents either a voltage or a current (other representations are possible also). It captures the non-conservative behavior of a set of interconnected components. Digital is a time-discrete and value- discrete signal. The interpretation of the signal values is described by the wireTypeDefs.

  • view_ref – A reference to a view in the file for which this type applies.

  • id

Parameters:
class ViewRef(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
id: str | None
signal_type: SignalTypeDefSignalType | None
view_ref: Iterable[ViewRef]
class org.accellera.ipxact.v1685_2022.SignalTypeDefSignalType(*values)

Bases: Enum

CONTINUOUS_CONSERVATIVE = 'continuous-conservative'
CONTINUOUS_NON_CONSERVATIVE = 'continuous-non-conservative'
DIGITAL = 'digital'
DISCRETE = 'discrete'
class org.accellera.ipxact.v1685_2022.SignalTypeDefs(signal_type_def=<factory>)

Bases: object

The group of signal type definitions.

Parameters:

signal_type_def (Iterable[SignalTypeDef])

signal_type_def: Iterable[SignalTypeDef]
class org.accellera.ipxact.v1685_2022.SignedLongintExpression(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: ComplexBaseExpression

An unsigned longint which supports an expression value.

Variables:

  • minimum – For elements which can be specified using expression which are supposed to be resolved to a signed longint value, this indicates the minimum value allowed.

  • maximum – For elements which can be specified using expression which are supposed to be resolved to a signed longint value, this indicates the maximum value allowed.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.SimpleAccessHandle(view_ref=<factory>, path_segments=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • view_ref – A list of views this accessHandle is applicable to. Note this element is optional, if it is not present the accessHandle applies to all views.

  • path_segments – An ordered list of pathSegment elements. When concatenated with a desired separator the elements in this form a HDL path for the parent slice into the referenced view.

  • vendor_extensions

  • id

Parameters:
class PathSegments(path_segment: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.path_segment_type.PathSegmentType] = <factory>)

Bases: object

Parameters:

path_segment (Iterable[PathSegmentType])

path_segment: Iterable[PathSegmentType]
class ViewRef(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
id: str | None
path_segments: PathSegments | None
vendor_extensions: VendorExtensions | None
view_ref: Iterable[ViewRef]
class org.accellera.ipxact.v1685_2022.SimpleClearboxType(*values)

Bases: Enum

INTERFACE = 'interface'
PIN = 'pin'
SIGNAL = 'signal'
class org.accellera.ipxact.v1685_2022.SimpleFileType(*values)

Bases: Enum

ASM_SOURCE = 'asmSource'
CPP_SOURCE = 'cppSource'
C_SOURCE = 'cSource'
EXECUTABLE_HDL = 'executableHdl'
E_SOURCE = 'eSource'
LIBERTY_SOURCE = 'libertySource'
OVASOURCE = 'OVASource'
PERL_SOURCE = 'perlSource'
PSL_SOURCE = 'pslSource'
SDC = 'SDC'
SPICE_SOURCE = 'spiceSource'
SVASOURCE = 'SVASource'
SW_OBJECT = 'swObject'
SW_OBJECT_LIBRARY = 'swObjectLibrary'
SYSTEM_CAMS_SOURCE = 'systemCAmsSource'
SYSTEM_CBINARY_LIBRARY = 'systemCBinaryLibrary'
SYSTEM_CSOURCE = 'systemCSource'
SYSTEM_CSOURCE_2_0 = 'systemCSource-2.0'
SYSTEM_CSOURCE_2_0_1 = 'systemCSource-2.0.1'
SYSTEM_CSOURCE_2_1 = 'systemCSource-2.1'
SYSTEM_CSOURCE_2_2 = 'systemCSource-2.2'
SYSTEM_CSOURCE_2_3 = 'systemCSource-2.3'
SYSTEM_RDL = 'systemRDL'
SYSTEM_RDL_1_0 = 'systemRDL-1.0'
SYSTEM_RDL_2_0 = 'systemRDL-2.0'
SYSTEM_VERILOG_SOURCE = 'systemVerilogSource'
SYSTEM_VERILOG_SOURCE_2009 = 'systemVerilogSource-2009'
SYSTEM_VERILOG_SOURCE_2012 = 'systemVerilogSource-2012'
SYSTEM_VERILOG_SOURCE_2017 = 'systemVerilogSource-2017'
SYSTEM_VERILOG_SOURCE_3_0 = 'systemVerilogSource-3.0'
SYSTEM_VERILOG_SOURCE_3_1 = 'systemVerilogSource-3.1'
SYSTEM_VERILOG_SOURCE_3_1A = 'systemVerilogSource-3.1a'
TCL_SOURCE = 'tclSource'
UNELABORATED_HDL = 'unelaboratedHdl'
UNKNOWN = 'unknown'
USER = 'user'
VERA_SOURCE = 'veraSource'
VERILOG_AMS_SOURCE = 'verilogAmsSource'
VERILOG_BINARY_LIBRARY = 'verilogBinaryLibrary'
VERILOG_SOURCE = 'verilogSource'
VERILOG_SOURCE_2001 = 'verilogSource-2001'
VERILOG_SOURCE_2005 = 'verilogSource-2005'
VERILOG_SOURCE_95 = 'verilogSource-95'
VHDL_AMS_SOURCE = 'vhdlAmsSource'
VHDL_BINARY_LIBRARY = 'vhdlBinaryLibrary'
VHDL_SOURCE = 'vhdlSource'
VHDL_SOURCE_2002 = 'vhdlSource-2002'
VHDL_SOURCE_2008 = 'vhdlSource-2008'
VHDL_SOURCE_87 = 'vhdlSource-87'
VHDL_SOURCE_93 = 'vhdlSource-93'
class org.accellera.ipxact.v1685_2022.SimplePortAccessType(*values)

Bases: Enum

PTR = 'ptr'
REF = 'ref'
class org.accellera.ipxact.v1685_2022.SingleShotDriver(single_shot_offset=None, single_shot_value=None, single_shot_duration=None)

Bases: object

Describes a driven one-shot port.

Variables:

  • single_shot_offset – Time in nanoseconds until start of one- shot.

  • single_shot_value – Value of port after first edge of one- shot.

  • single_shot_duration – Duration in nanoseconds of the one shot.

Parameters:
class SingleShotDuration(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[float] = None, maximum: Optional[float] = None, units: org.accellera.ipxact.v1685_2022.delay_value_unit_type.DelayValueUnitType = <DelayValueUnitType.NS: 'ns'>)

Bases: RealExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

  • units (DelayValueUnitType)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
units: DelayValueUnitType
value: str
class SingleShotOffset(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[float] = None, maximum: Optional[float] = None, units: org.accellera.ipxact.v1685_2022.delay_value_unit_type.DelayValueUnitType = <DelayValueUnitType.NS: 'ns'>)

Bases: RealExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (float | None)

  • maximum (float | None)

  • units (DelayValueUnitType)

maximum: float | None
minimum: float | None
other_attributes: Mapping[str, str]
units: DelayValueUnitType
value: str
single_shot_duration: SingleShotDuration | None
single_shot_offset: SingleShotOffset | None
single_shot_value: UnsignedBitVectorExpression | None
class org.accellera.ipxact.v1685_2022.SliceType(path_segments=None, range=None, id=None)

Bases: object

Contains the HDL path information for a slice of the IP-XACT object.

Variables:

  • path_segments – An ordered list of pathSegment elements. When concatenated with a desired separator the elements in this form a HDL path for the parent slice into the referenced view.

  • range – A range to be applied to the concatenation of the above path segments

  • id

Parameters:
class PathSegments(path_segment: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.path_segment_type.PathSegmentType] = <factory>)

Bases: object

Parameters:

path_segment (Iterable[PathSegmentType])

path_segment: Iterable[PathSegmentType]
id: str | None
path_segments: PathSegments | None
range: Range | None
class org.accellera.ipxact.v1685_2022.SlicedAccessHandle(view_ref=<factory>, slices=None, vendor_extensions=None, force=True, id=None)

Bases: object

Variables:

  • view_ref – A list of views this accessHandle is applicable to. Note this element is optional, if it is not present the accessHandle applies to all views.

  • slices

  • vendor_extensions

  • force

  • id

Parameters:
class ViewRef(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
force: bool
id: str | None
slices: SlicesType | None
vendor_extensions: VendorExtensions | None
view_ref: Iterable[ViewRef]
class org.accellera.ipxact.v1685_2022.SlicesType(slice=<factory>, id=None)

Bases: object

Each slice specifies the HDL path for part of the parent IP-XACT object.

The slices must be concatenated to calculate the entire path. If there is only one slice, it is assumed to be the path for the entire IP-XACT object.

Variables:

  • slice – The HDL path for a slice of the IP-XACT object.

  • id

Parameters:

  • slice (Iterable[SliceType])

  • id (str | None)

id: str | None
slice: Iterable[SliceType]
class org.accellera.ipxact.v1685_2022.Stride(value: str = '', other_attributes: collections.abc.Mapping[str, str] = <factory>, minimum: Optional[int] = None, maximum: Optional[int] = None, id: Optional[str] = None)

Bases: UnsignedPositiveLongintExpression

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

  • id (str | None)

id: str | None
maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.StringExpression(value='', other_attributes=<factory>)

Bases: ComplexBaseExpression

Represents a string.

It supports an expression value.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.StructPortTypeDefs(struct_port_type_def: collections.abc.Iterable['StructPortTypeDefs.StructPortTypeDef'] = <factory>)

Bases: object

Parameters:

struct_port_type_def (Iterable[StructPortTypeDef])

class StructPortTypeDef(type_name=None, type_definition=<factory>, type_parameters=None, role=None, view_ref=<factory>, id=None)

Bases: object

Variables:

  • type_name

  • type_definition – Where the definition of the type is contained. For SystemC and SystemVerilog it is the include file containing the type definition.

  • type_parameters

  • role – Indicates the role that this structured port plays in the connection. Only valid for structured ports with structType=’interface’. In SystemVerilog, this indicates the modport for the SystemVerilog interface corresponding to this structuredPortType.

  • view_ref – A reference to a view name in the file for which this type applies.

  • id

Parameters:
class TypeDefinition(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
class TypeName(value='', constrained=<factory>)

Bases: object

Variables:

  • value

  • constrained – Defines the types for the port has constrained the number of bits in the vector

Parameters:

  • value (str)

  • constrained (Iterable[str])

constrained: Iterable[str]
value: str
class TypeParameters(type_parameter: collections.abc.Iterable[org.accellera.ipxact.v1685_2022.type_parameter.TypeParameter] = <factory>)

Bases: object

Parameters:

type_parameter (Iterable[TypeParameter])

type_parameter: Iterable[TypeParameter]
class ViewRef(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
id: str | None
role: str | None
type_definition: Iterable[TypeDefinition]
type_name: TypeName | None
type_parameters: TypeParameters | None
view_ref: Iterable[ViewRef]
struct_port_type_def: Iterable[StructPortTypeDef]
class org.accellera.ipxact.v1685_2022.SubPortReference(part_select=None, sub_port_ref=None, id=None)

Bases: object

Variables:

  • part_select

  • sub_port_ref – A subPort on the referenced structured port.

  • id

Parameters:

  • part_select (PartSelect | None)

  • sub_port_ref (str | None)

  • id (str | None)

id: str | None
part_select: PartSelect | None
sub_port_ref: str | None
class org.accellera.ipxact.v1685_2022.SubPortType(name=None, display_name=None, short_description=None, description=None, wire=None, structured=None, arrays=None, access=None, vendor_extensions=None, id=None, is_io=None)

Bases: object

A port description, giving a name and an access type for high level ports.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • wire – Defines a port whose type resolves to simple bits.

  • structured

  • arrays

  • access – Port access characteristics.

  • vendor_extensions

  • id

  • is_io – When present and set to ‘true’ identifies this port as being an I/O to the containing structure port type. Only valid for subPorts contained in a structured port with structType=’interface’.

Parameters:
access: PortAccessType1 | None
arrays: Arrays | None
description: Description | None
display_name: DisplayName | None
id: str | None
is_io: bool | None
name: str | None
short_description: ShortDescription | None
structured: PortStructuredType | None
vendor_extensions: VendorExtensions | None
wire: PortWireType | None
class org.accellera.ipxact.v1685_2022.SubspaceMap(name=None, display_name=None, short_description=None, description=None, base_address=None, parameters=None, vendor_extensions=None, initiator_ref=None, segment_ref=None, id=None)

Bases: SubspaceRefType

Maps in an address subspace from across a bus bridge.

Its initiatorRef attribute refers by name to the initiator bus interface on the other side of the bridge. It must match the initiatorRef attribute of a bridge element on the target interface, and that bridge element must be designated as opaque.

Parameters:
base_address: SignedLongintExpression | None
description: Description | None
display_name: DisplayName | None
id: str | None
initiator_ref: str | None
name: str | None
parameters: Parameters | None
segment_ref: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.SubspaceRefType(name=None, display_name=None, short_description=None, description=None, base_address=None, parameters=None, vendor_extensions=None, initiator_ref=None, segment_ref=None, id=None)

Bases: object

Address subspace type.

Its subspaceReference attribute references the subspace from which the dimensions are taken.

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • base_address – Base of a subspace map. Expressed as the number of addressable units from the containing memoryMap.

  • parameters – Any parameters that may apply to the subspace reference.

  • vendor_extensions

  • initiator_ref – For subspaceMap elements, this attribute identifies the initiator that contains the address space to be mapped.

  • segment_ref – Refernce to a segment of the addressSpace of the initiatorRef attribute.

  • id

Parameters:
base_address: SignedLongintExpression | None
description: Description | None
display_name: DisplayName | None
id: str | None
initiator_ref: str | None
name: str | None
parameters: Parameters | None
segment_ref: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.TestableTestConstraint(*values)

Bases: Enum

READ_ONLY = 'readOnly'
RESTORE = 'restore'
UNCONSTRAINED = 'unconstrained'
WRITE_AS_READ = 'writeAsRead'
class org.accellera.ipxact.v1685_2022.TimingConstraint(value=None, clock_edge=None, delay_type=None, clock_name=None, id=None)

Bases: object

Defines a timing constraint for the associated port.

The constraint is relative to the clock specified by the clockName attribute. The clockEdge indicates which clock edge the constraint is associated with (default is rising edge). The delayType attribute can be specified to further refine the constraint.

Variables:

  • value

  • clock_edge – Indicates the clock edge that a timing constraint is relative to.

  • delay_type – Indicates the type of delay in a timing constraint - minimum or maximum.

  • clock_name – Indicates the name of the clock to which this constraint applies.

  • id

Parameters:
clock_edge: EdgeValueType | None
clock_name: str | None
delay_type: DelayValueType | None
id: str | None
value: float | None
class org.accellera.ipxact.v1685_2022.TransTypeDef(type_name=None, type_definition=<factory>, type_parameters=None, view_ref=<factory>, id=None)

Bases: object

Definition of a single transactional type defintion.

Variables:

  • type_name – The name of the port type. Can be any predefined type such sc_port or sc_export in SystemC or any user-defined type such as tlm_port.

  • type_definition – Where the definition of the type is contained. For SystemC and SystemVerilog it is the include file containing the type definition.

  • type_parameters

  • view_ref – A reference to a view name in the file for which this type applies.

  • id

Parameters:
class TypeDefinition(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
class TypeName(value='', exact=True)

Bases: object

Variables:

  • value

  • exact – When false, defines that the type is an abstract type that may not be related to an existing type in the language of the referenced view.

Parameters:

  • value (str)

  • exact (bool)

exact: bool
value: str
class ViewRef(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
id: str | None
type_definition: Iterable[TypeDefinition]
type_name: TypeName | None
type_parameters: TypeParameters | None
view_ref: Iterable[ViewRef]
class org.accellera.ipxact.v1685_2022.TransTypeDefs(trans_type_def=<factory>)

Bases: object

The group of transactional type definitions.

If no match to a viewName is found then the default language types are to be used. See the User Guide for these default types.

Parameters:

trans_type_def (Iterable[TransTypeDef])

trans_type_def: Iterable[TransTypeDef]
class org.accellera.ipxact.v1685_2022.TransactionalPowerConstraintType(power_domain_ref: org.accellera.ipxact.v1685_2022.power_domain_ref.PowerDomainRef | None = None, vendor_extensions: org.accellera.ipxact.v1685_2022.vendor_extensions.VendorExtensions | None = None, id: str | None = None)

Bases: object

Parameters:
id: str | None
power_domain_ref: PowerDomainRef | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.TransparentBridge(vendor_extensions=None, initiator_ref=None, id=None)

Bases: object

If this element is present, it indicates that the bus interface provides a transparent bridge to another initiator bus interface on the same component.

It has a initiatorRef attribute which contains the name of the other bus interface. Any target interface can bridge to multiple initiator interfaces, and multiple target interfaces can bridge to the same initiator interface.

Variables:

  • vendor_extensions

  • initiator_ref – The name of the initiator bus interface to which this interface bridges.

  • id

Parameters:

  • vendor_extensions (VendorExtensions | None)

  • initiator_ref (str | None)

  • id (str | None)

id: str | None
initiator_ref: str | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.TransportMethodType(*values)

Bases: Enum

FILE = 'file'
class org.accellera.ipxact.v1685_2022.TypeDefinitions(vendor=None, library=None, name=None, version=None, display_name=None, short_description=None, description=None, external_type_definitions=<factory>, modes=None, views=None, field_access_policy_definitions=None, enumeration_definitions=None, field_definitions=None, register_definitions=None, register_file_definitions=None, address_block_definitions=None, bank_definitions=None, memory_map_definitions=None, memory_remap_definitions=None, reset_types=None, choices=None, parameters=None, assertions=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • vendor – Name of the vendor who supplies this file.

  • library – Name of the logical library this element belongs to.

  • name – The name of the object.

  • version – Indicates the version of the named element.

  • display_name – Name for display purposes. Typically a few words providing a more detailed and/or user-friendly name than the vlnv.

  • short_description

  • description

  • external_type_definitions

  • modes – A list of user defined component modes.

  • views – A list of user defined views.

  • field_access_policy_definitions

  • enumeration_definitions

  • field_definitions

  • register_definitions

  • register_file_definitions

  • address_block_definitions

  • bank_definitions

  • memory_map_definitions

  • memory_remap_definitions

  • reset_types – A list of user defined resetTypes applicable to this component.

  • choices

  • parameters

  • assertions

  • vendor_extensions

  • id

Parameters:
class Modes(mode: collections.abc.Iterable['TypeDefinitions.Modes.Mode'] = <factory>)

Bases: object

Parameters:

mode (Iterable[Mode])

class Mode(name=None, display_name=None, short_description=None, description=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • vendor_extensions

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
mode: Iterable[Mode]
class ResetTypes(reset_type=<factory>)

Bases: object

Variables:

reset_type – A user defined reset policy

Parameters:

reset_type (Iterable[ResetType])

class ResetType(name=None, display_name=None, short_description=None, description=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • vendor_extensions

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
reset_type: Iterable[ResetType]
class Views(view: collections.abc.Iterable['TypeDefinitions.Views.View'] = <factory>)

Bases: object

Parameters:

view (Iterable[View])

class View(name=None, display_name=None, short_description=None, description=None, vendor_extensions=None, id=None)

Bases: object

Variables:

  • name – Unique name

  • display_name

  • short_description

  • description

  • vendor_extensions

  • id

Parameters:
description: Description | None
display_name: DisplayName | None
id: str | None
name: str | None
short_description: ShortDescription | None
vendor_extensions: VendorExtensions | None
view: Iterable[View]
address_block_definitions: AddressBlockDefinitions | None
assertions: Assertions | None
bank_definitions: BankDefinitions | None
choices: Choices | None
description: Description | None
display_name: str | None
enumeration_definitions: EnumerationDefinitions | None
external_type_definitions: Iterable[ExternalTypeDefinitions]
field_access_policy_definitions: FieldAccessPolicyDefinitions | None
field_definitions: FieldDefinitions | None
id: str | None
library: str | None
memory_map_definitions: MemoryMapDefinitions | None
memory_remap_definitions: MemoryRemapDefinitions | None
modes: Modes | None
name: str | None
parameters: Parameters | None
register_definitions: RegisterDefinitions | None
register_file_definitions: RegisterFileDefinitions | None
reset_types: ResetTypes | None
short_description: ShortDescription | None
vendor: str | None
vendor_extensions: VendorExtensions | None
version: str | None
views: Views | None
class org.accellera.ipxact.v1685_2022.TypeParameter(name=None, display_name=None, short_description=None, description=None, vectors=None, arrays=None, value=None, vendor_extensions=None, id=None, parameter_id=None, prompt=None, choice_ref=None, order=None, config_groups=<factory>, minimum=None, maximum=None, type_value=FormatType.STRING, sign=None, prefix=None, unit=None, resolve=ModuleParameterTypeResolve.IMMEDIATE, other_attributes=<factory>, data_type=None, usage_type=ModuleParameterTypeUsageType.TYPED, data_type_definition=None, constrained=<factory>)

Bases: ModuleParameterType

A typed parameter name value pair.

The optional attribute dataType defines the type of the value and the usageType attribute indicates how the parameter is to be used.

Parameters:
class Vectors(vector=<factory>)

Bases: object

Variables:

vector – Left and right ranges of the vector.

Parameters:

vector (Iterable[Vector])

class Vector(left: org.accellera.ipxact.v1685_2022.left.Left | None = None, right: org.accellera.ipxact.v1685_2022.right.Right | None = None, vector_id: str | None = None, id: str | None = None)

Bases: object

Parameters:

  • left (Left | None)

  • right (Right | None)

  • vector_id (str | None)

  • id (str | None)

id: str | None
left: Left | None
right: Right | None
vector_id: str | None
vector: Iterable[Vector]
arrays: ModuleParameterArrays | None
choice_ref: str | None
config_groups: Iterable[str]
constrained: Iterable[str]
data_type: str | None
data_type_definition: str | None
description: Description | None
display_name: DisplayName | None
id: str | None
maximum: str | None
minimum: str | None
name: str | None
order: float | None
other_attributes: Mapping[str, str]
parameter_id: str | None
prefix: ModuleParameterTypePrefix | None
prompt: str | None
resolve: ModuleParameterTypeResolve
short_description: ShortDescription | None
sign: SignType | None
type_value: FormatType
unit: ModuleParameterTypeUnit | None
usage_type: ModuleParameterTypeUsageType
value: Value | None
vectors: 'ModuleParameterType.Vectors' | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.TypeParameters(type_parameter=<factory>, service_type_def=<factory>)

Bases: object

List of port type parameters (e.g. template or constructor parameters for a systemC port or socket)

Parameters:
service_type_def: Iterable[ServiceTypeDef]
type_parameter: Iterable[TypeParameter]
class org.accellera.ipxact.v1685_2022.UnresolvedStringExpression(value='', other_attributes=<factory>)

Bases: ComplexBaseExpression

Represents a string which cannot be fully resolved.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.UnresolvedUnsignedBitExpression(value='', other_attributes=<factory>)

Bases: ComplexBaseExpression

Unsigned Bit Expression which cannot be fully resolved.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.UnresolvedUnsignedPositiveIntExpression(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: ComplexBaseExpression

An positive unsigned int which supports an expression value.

Variables:

  • minimum – For elements which can be specified using expression which are supposed to be resolved to an unsiged int value, this indicates the minimum value allowed.

  • maximum – For elements which can be specified using expression which are supposed to be resolved to a unsigned int value, this indicates the maximum value allowed.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.UnsignedBitExpression(value='', other_attributes=<factory>)

Bases: ComplexBaseExpression

Represents a single-bit/bool.

It supports an expression value.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.UnsignedBitVectorExpression(value='', other_attributes=<factory>)

Bases: ComplexBaseExpression

Represents a bit-string.

It supports an expression value.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.UnsignedIntExpression(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: ComplexBaseExpression

An unsigned int which supports an expression value.

Variables:

  • minimum – For elements which can be specified using expression which are supposed to be resolved to an unsiged int value, this indicates the minimum value allowed.

  • maximum – For elements which can be specified using expression which are supposed to be resolved to a unsigned int value, this indicates the maximum value allowed.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.UnsignedLongintExpression(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: ComplexBaseExpression

An unsigned longint which supports an expression value.

Variables:

  • minimum – For elements which can be specified using expression which are supposed to be resolved to a unsigend longint value, this indicates the minimum value allowed.

  • maximum – For elements which can be specified using expression which are supposed to be resolved to an unsigend longint value, this indicates the maximum value allowed.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.UnsignedPositiveIntExpression(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: ComplexBaseExpression

An positive unsigned int which supports an expression value.

Variables:

  • minimum – For elements which can be specified using expression which are supposed to be resolved to an unsiged int value, this indicates the minimum value allowed.

  • maximum – For elements which can be specified using expression which are supposed to be resolved to a unsigned int value, this indicates the maximum value allowed.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.UnsignedPositiveLongintExpression(value='', other_attributes=<factory>, minimum=None, maximum=None)

Bases: ComplexBaseExpression

A positive unsigned longint which supports an expression value.

Variables:

  • minimum – For elements which can be specified using expression which are supposed to be resolved to a positive unsigned longint value, this indicates the minimum value allowed.

  • maximum – For elements which can be specified using expression which are supposed to be resolved to a positive unsigned longint value, this indicates the maximum value allowed.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str
class org.accellera.ipxact.v1685_2022.UsageType(*values)

Bases: Enum

Describes the usage of an address block.

Variables:

  • MEMORY – Denotes an address range that can be used for read- write or read-only data storage.

  • REGISTER – Denotes an address block that is used to communicate with hardware.

  • RESERVED – Denotes an address range that must remain unoccupied.

MEMORY = 'memory'
REGISTER = 'register'
RESERVED = 'reserved'
class org.accellera.ipxact.v1685_2022.Vector(left=None, right=None, id=None)

Bases: object

Left and right ranges of the vector.

Parameters:

  • left (Left | None)

  • right (Right | None)

  • id (str | None)

id: str | None
left: Left | None
right: Right | None
class org.accellera.ipxact.v1685_2022.Vectors(vector=<factory>)

Bases: object

Vectored information.

Parameters:

vector (Iterable[Vector])

vector: Iterable[Vector]
class org.accellera.ipxact.v1685_2022.VendorExtensions(any_element=<factory>)

Bases: object

Container for vendor specific extensions.

Variables:

any_element – Accepts any element(s) the content provider wants to put here, including elements from the ipxact namespace.

Parameters:

any_element (Iterable[object])

any_element: Iterable[object]

Bases: object

A set of links between internal and external views defined in the typeDefinitions document.

Variables:

view_link – A link between one external view and one internal view.

Parameters:

view_link (Iterable[ViewLink])

Bases: object

Variables:

  • external_view_reference – Reference to a view defined in the linked external type definitions.

  • view_reference – Reference to a view defined internally.

  • vendor_extensions

  • id

Parameters:
class ExternalViewReference(view_ref=None)

Bases: object

Variables:

view_ref – Reference to a specific view.

Parameters:

view_ref (str | None)

view_ref: str | None
class ViewReference(view_ref=None)

Bases: object

Variables:

view_ref – Reference to a specific view.

Parameters:

view_ref (str | None)

view_ref: str | None
external_view_reference: ExternalViewReference | None
id: str | None
vendor_extensions: VendorExtensions | None
view_reference: ViewReference | None
class org.accellera.ipxact.v1685_2022.ViewRef(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
class org.accellera.ipxact.v1685_2022.Volatile(value=None)

Bases: object

Indicates whether the data is volatile.

Parameters:

value (bool | None)

value: bool | None
class org.accellera.ipxact.v1685_2022.Wire(qualifier=None, on_system=<factory>, on_initiator=None, on_target=None, default_value=None, requires_driver=None)

Bases: object

A port that carries logic or an array of logic values.

Variables:

  • qualifier – The type of information this port carries A wire port can carry both address and data, but may not mix this with a clock or reset

  • on_system – Defines constraints for this port when present in a system bus interface with a matching group name.

  • on_initiator – Defines constraints for this port when present in a initiator bus interface.

  • on_target – Defines constraints for this port when present in a target bus interface.

  • default_value – Indicates the default value for this wire port.

  • requires_driver

Parameters:
class OnInitiator(presence=None, width=None, direction=None, mode_constraints=None, mirrored_mode_constraints=None)

Bases: object

Variables:

  • presence

  • width – Number of bits required to represent this port. Absence of this element indicates unconstrained number of bits, i.e. the component will define the number of bits in this port. The logical numbering of the port starts at 0 to width-1.

  • direction – If this element is present, the direction of this port is restricted to the specified value. The direction is relative to the non-mirrored interface.

  • mode_constraints – Specifies default constraints for the enclosing wire type port. If the mirroredModeConstraints element is not defined, then these constraints applied to this port when it appears in a ‘mode’ bus interface or a mirrored-‘mode’ bus interface. Otherwise they only apply when the port appears in a ‘mode’ bus interface.

  • mirrored_mode_constraints – Specifies default constraints for the enclosing wire type port when it appears in a mirrored-‘mode’ bus interface.

Parameters:
class Width(value='', other_attributes=<factory>, minimum=None, maximum=None, all_bits=False)

Bases: UnsignedPositiveIntExpression

Variables:

all_bits – false: mapping is optional, any number of bits can be mapped. true: mapping is required the full width is supposed to be mapped.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

  • all_bits (bool)

all_bits: bool
maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str
direction: Direction | None
mirrored_mode_constraints: AbstractionDefPortConstraintsType | None
mode_constraints: AbstractionDefPortConstraintsType | None
presence: Presence | None
width: Width | None
class OnSystem(group=None, presence=None, width=None, direction=None, mode_constraints=None, mirrored_mode_constraints=None, id=None)

Bases: object

Variables:

  • group – Used to group system ports into different groups within a common bus.

  • presence

  • width – Number of bits required to represent this port. Absence of this element indicates unconstrained number of bits, i.e. the component will define the number of bits in this port. The logical numbering of the port starts at 0 to width-1.

  • direction – If this element is present, the direction of this port is restricted to the specified value. The direction is relative to the non-mirrored interface.

  • mode_constraints – Specifies default constraints for the enclosing wire type port. If the mirroredModeConstraints element is not defined, then these constraints applied to this port when it appears in a ‘mode’ bus interface or a mirrored-‘mode’ bus interface. Otherwise they only apply when the port appears in a ‘mode’ bus interface.

  • mirrored_mode_constraints – Specifies default constraints for the enclosing wire type port when it appears in a mirrored-‘mode’ bus interface.

  • id

Parameters:
class Width(value='', other_attributes=<factory>, minimum=None, maximum=None, all_bits=False)

Bases: UnsignedPositiveIntExpression

Variables:

all_bits – false: mapping is optional, any number of bits can be mapped. true: mapping is required the full width is supposed to be mapped.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

  • all_bits (bool)

all_bits: bool
maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str
direction: Direction | None
group: str | None
id: str | None
mirrored_mode_constraints: AbstractionDefPortConstraintsType | None
mode_constraints: AbstractionDefPortConstraintsType | None
presence: Presence | None
width: Width | None
class OnTarget(presence=None, width=None, direction=None, mode_constraints=None, mirrored_mode_constraints=None)

Bases: object

Variables:

  • presence

  • width – Number of bits required to represent this port. Absence of this element indicates unconstrained number of bits, i.e. the component will define the number of bits in this port. The logical numbering of the port starts at 0 to width-1.

  • direction – If this element is present, the direction of this port is restricted to the specified value. The direction is relative to the non-mirrored interface.

  • mode_constraints – Specifies default constraints for the enclosing wire type port. If the mirroredModeConstraints element is not defined, then these constraints applied to this port when it appears in a ‘mode’ bus interface or a mirrored-‘mode’ bus interface. Otherwise they only apply when the port appears in a ‘mode’ bus interface.

  • mirrored_mode_constraints – Specifies default constraints for the enclosing wire type port when it appears in a mirrored-‘mode’ bus interface.

Parameters:
class Width(value='', other_attributes=<factory>, minimum=None, maximum=None, all_bits=False)

Bases: UnsignedPositiveIntExpression

Variables:

all_bits – false: mapping is optional, any number of bits can be mapped. true: mapping is required the full width is supposed to be mapped.

Parameters:

  • value (str)

  • other_attributes (Mapping[str, str])

  • minimum (int | None)

  • maximum (int | None)

  • all_bits (bool)

all_bits: bool
maximum: int | None
minimum: int | None
other_attributes: Mapping[str, str]
value: str
direction: Direction | None
mirrored_mode_constraints: AbstractionDefPortConstraintsType | None
mode_constraints: AbstractionDefPortConstraintsType | None
presence: Presence | None
width: Width | None
default_value: UnsignedBitVectorExpression | None
on_initiator: OnInitiator | None
on_system: Iterable[OnSystem]
on_target: OnTarget | None
qualifier: QualifierType | None
requires_driver: RequiresDriver | None
class org.accellera.ipxact.v1685_2022.WirePowerConstraintType(power_domain_ref: org.accellera.ipxact.v1685_2022.power_domain_ref.PowerDomainRef | None = None, range: org.accellera.ipxact.v1685_2022.range.Range | None = None, vendor_extensions: org.accellera.ipxact.v1685_2022.vendor_extensions.VendorExtensions | None = None, id: str | None = None)

Bases: object

Parameters:
id: str | None
power_domain_ref: PowerDomainRef | None
range: Range | None
vendor_extensions: VendorExtensions | None
class org.accellera.ipxact.v1685_2022.WireTypeDef(type_name=None, type_definition=<factory>, view_ref=<factory>, id=None)

Bases: object

Definition of a single wire type defintion that can relate to multiple views.

Variables:

  • type_name – The name of the logic type. Examples could be std_logic, std_ulogic, std_logic_vector, sc_logic, …

  • type_definition – Where the definition of the type is contained. For std_logic, this is contained in IEEE.std_logic_1164.all. For sc_logic, this is contained in systemc.h. For VHDL this is the library and package as defined by the “used” statement. For SystemC and SystemVerilog it is the include file required. For verilog this is not needed.

  • view_ref – A reference to a view name in the file for which this type applies.

  • id

Parameters:
class TypeDefinition(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
class TypeName(value='', constrained=<factory>)

Bases: object

Variables:

  • value

  • constrained – Defines the types for the port has constrained the number of bits in the vector

Parameters:

  • value (str)

  • constrained (Iterable[str])

constrained: Iterable[str]
value: str
class ViewRef(value: str = '', id: str | None = None)

Bases: object

Parameters:

  • value (str)

  • id (str | None)

id: str | None
value: str
id: str | None
type_definition: Iterable[TypeDefinition]
type_name: TypeName | None
view_ref: Iterable[ViewRef]
class org.accellera.ipxact.v1685_2022.WireTypeDefs(wire_type_def=<factory>)

Bases: object

The group of wire type definitions.

If no match to a viewName is found then the default language types are to be used. See the User Guide for these default types.

Parameters:

wire_type_def (Iterable[WireTypeDef])

wire_type_def: Iterable[WireTypeDef]
class org.accellera.ipxact.v1685_2022.WriteValueConstraint(write_as_read=None, use_enumerated_values=None, minimum=None, maximum=None)

Bases: WriteValueConstraintType

The legal values that may be written to a field.

If not specified the legal values are not specified.

Parameters:
maximum: UnsignedBitVectorExpression | None
minimum: UnsignedBitVectorExpression | None
use_enumerated_values: bool | None
write_as_read: bool | None
class org.accellera.ipxact.v1685_2022.WriteValueConstraintType(write_as_read=None, use_enumerated_values=None, minimum=None, maximum=None)

Bases: object

A constraint on the values that can be written to this field.

Absence of this element implies that any value that fits can be written to it.

Variables:

  • write_as_read – writeAsRead indicates that only a value immediately read before a write is a legal value to be written.

  • use_enumerated_values – useEnumeratedValues indicates that only write enumeration value shall be legal values to be written.

  • minimum – The minimum legal value that may be written to a field

  • maximum – The maximum legal value that may be written to a field

Parameters:
maximum: UnsignedBitVectorExpression | None
minimum: UnsignedBitVectorExpression | None
use_enumerated_values: bool | None
write_as_read: bool | None